Why Using The Device Multiplier Can Make Your Monte Carlo Simulations Wrong

Matching and Mismatch

One of the key concepts that differentiates analog IC design from discrete circuit analog design is the matching concept. Devices fabricated at the same time, under the same conditions, and very close to each other will have almost the same parameters, i.e., will be matched. This key property is what enables us to build the analog IC design building blocks such as current mirrors and differential pairs.

But since nothing in life is perfect, we will still have a small mismatch error. By using good layout matching techniques such as interdigitation and dummies, designers can reduce the systematic mismatch. However, a random mismatch component will always be there. The most important mismatch error for CMOS analog circuits is the mismatch in the threshold voltage (VT). The standard deviation of the random mismatch error is inversely proportional to the square root of the device area (W*L) as given by Pelgrom's model

Standard deviation of VT = σ(VT) = A_VT/sqrt(W*L)
Where A_VT is a technology parameter (Pelgrom's coefficient)

The standard deviation of the drain current is given by

Standard deviation of ID = σ(ID) = σ(VT)*gm

And the normalized standard deviation is given by

Normalized standard deviation of ID = σ(ID)/ID = σ(VT)*gm/ID

Where the attentive reader will notice the popular (gm/ID) design knob in the equation. It is clear that using a small gm/ID, i.e., biasing in strong inversion, will be beneficial in this case.

Current Mirror Sizing Trade-offs

Let's take a simple design example to illustrate mismatch analysis, design and simulation. Assume we want to design a simple current mirror circuit given the parameters below.

A_VT = 3.5 mV-um
Ibias = 100 uA
Mirroring ratio = 1
σ(ID)/ID = 1 %

Noting that there are two transistors contributing to the error in the output current, σ(ID)/ID will be given by

σ(ID)/ID = sqrt(2)*σ(VT)*gm/ID ≈ 1%

where the sqrt(2) factor is because the variation in each transistor is an independent and identically distributed (i.i.d) random variable, i.e., for uncorrelated random variables, we add the variances not the standard deviations.

Using the Sizing Assistant (SA) tool by Master Micro, we can perform a unique sweep at a constant σ(ID)/ID by setting the parameters as shown below. This will perform an unconventional sweep of gm/ID from 5 to 20 at σ(ID)/ID = 1%.

Hint: The above example used a simple Pelgrom's model for the purpose of illustration. The Analog Designer's Toolbox (ADT) can characterize the mismatch of the device as a black box regardless of the model complexity and store it in the idmis parameter in the LUTs. The mismatch percentage can be then written as σ(ID)/ID = sqrt(2)*idmis/ID ≈ 1%.

It should be noted that every point in this sweep will have different L and W, thus, this sweep of gm/ID at a constant mismatch cannot be performed using a conventional simulator. In a fraction of a second, the Sizing Assistant (SA) sweep results can be plotted as shown below.

From the above Sizing Assistant (SA) results, it is clear that the smallest gm/ID (biasing in Strong Inversion, SI) is desirable from the perspective of area and VDS dependence (λ). Thus, the minimum gm/ID will be limited by the required minimum output voltage (the compliance voltage of the current source), where we assume VDSmin ≈ VDsat ≈ V* = 2/(gm/ID).

Hint: In some technologies, the mismatch may be partially independent of L due to non-uniform channel doping. In this case, mismatch can be reduced by increasing W (biasing in Weak Inversion, WI) or by stacking several devices. Biasing in WI may be also necessary in low voltage circuits that have limited headroom

Assume we select the design point highlighted by the cursor in the above figure and we will round the selected numbers to L = 1um and W = 20um. The current mirror testbench is shown below.

Monte Carlo Simulations

Using Monte Carlo (MC) simulation to study mismatch in analog circuits is an essential tool for analog IC designers. In this example, we run 500 points of MC simulation (choose variation = mismatch in the MC simulation settings). The results are exactly as expected as shown below, with σ(ID) ≈ 1 uA, i.e., σ(ID)/ID ≈ 1%.

Due to layout considerations, the device is usually divided into unit elements connected in parallel. Assume we will break our 20 um device into four 5 um unit transistors. A method that is sometimes used is to draw the unit device in the schematic only once, then set its multiplier parameter (m) to 4. The new schematic is shown below.

If we run exactly the same testbench, the result will be completely unexpected! The mismatch doubles as shown below (σ(ID)/ID ≈ 2%)!

How to explain this puzzle? The answer to this puzzle is the definition of the multiplier (m) parameter. The multiplier simply means that the simulator multiplies the current by this number. Actually, some simulators allows m to be a fraction! Thus, the errors of the four unit devices will be exactly correlated, and σ(ID)/ID will be given by

σ(ID)/ID = sqrt(2)*4*A_VT/sqrt(W/4*L)*(gm/4)/ID 
         = sqrt(2)*2*A_VT/sqrt(W*L)*gm/ID 
         ≈ 2%

Of course this result is wrong, because the unit devices are actually uncorrelated. Then, what is the correct way of building the schematic? Drawing four unit devices in parallel is cumbersome and unpleasant. The good news is that there is a smart and elegant solution to this problem, which is naming the device as an array of devices, i.e., instead of naming the device M0 and setting m = 4, we can simply name it M0<3:0> and set m = 1. This will guarantee that we have four uncorrelated unit devices as shown in the schematic below.

Now let's run our MC mismatch testbench again. Congratulations! The result is back to 1% as shown below, which is the correct value!

Hint: The Sizing Assistant is best suited for visualizing and optimizing the properties of one or few transistors. Mismatch optimization of a more complex circuit can be done using ADT design space exploration feature.

Mismatch Models

Do all mismatch models suffer from this problem? The answer is no. A good mismatch model (which is usually present in a commercial PDK) will solve the above problem through the following tricks in the model file:

1) Avoid using the built-in multiplier parameter 'm' in the parameters of the subcircuit (macro model) which includes the device mismatch model. Instead, use any other arbitrary name, e.g., 'mult'.

.subckt nch_mis (d g s b) w=10u l=0.18u mult=1

2) Pass the defined multiplier (e.g., 'mult') to the built-in multiplier parameter 'm' of the intrinsic device model.

MN (d g s b) nch w=w l=l m=mult

3) Include the defined multiplier (e.g., 'mult') in the standard deviation equation to fix the correlation effect discussed above.

.param dvth = 'avt / sqrt(mult * l * w * 1e12) * unit_distn'

Finally...

The take home message is: Be cautious when you use the built-in multiplier ('m') parameter! It may give wrong results for your MC mismatch testbench, especially if you use a crude model!

Would you like to enjoy using the Sizing Assistant (SA) to size your devices intuitively and generate instant designer-oriented charts? Contact us to get your free trial!

Would you like to replicate the results in this article? You can use this model file.

Thanks!

#adt_wiki #mastermicro #adt #mastering_microelectronics #analog #analogdesign #analogicdesign #vlsi #cmos #microelectronics #electronics #engineering #technology