Intel Business’ Post

View organization page for Intel Business, graphic

149,672 followers

Making waves across the tech world 🌊 Since announcing at #Computex, everyone is excited about our #IntelXeon 6 processors with Efficient-cores. What excites you about this latest generation of processors?

  • No alternative text description for this image
  • No alternative text description for this image
  • No alternative text description for this image
Jeff Morrison

Financial Cultural Operational and Technical Consultant - Alpha Sense Financial Consulting

6d

When do you expect to reach parity in terms of ISO yields. Ireland is reporting Intel 4 and 3 aren't ready for primetime. TSMC is at an average weekly ISO of 670. For a 12mm x 12mm die this translates to 120% more good die on 3nm. The process isn't well characterized and the TSMC folks say your at a local maximum They've comprehensively examined the response surface and feel they are near a global maximum and have better control of the E-test parameter and each layers critical dimensions have 6 sigma control. We reckon that you're at 4.2 for the 3nm, and haven't optimized the target CD's especially on the critical gate layer and ultra fine pitch metal layers. Also registration between layers with stacked tolerance is a big limiting factor to better CD's. What's the recovery plan to get economicallly viable utilization and yields. With equipment utilization at sub 50% and yields less than 45% your true over all productivity is less than 25%. TSMC has 90% utilization and approximately 85% yields they are realizing roughly 80% productivity in their 3nm factories. Our models show Foundry losses growing 12% Moreover your transistor density on 3nm is 25 to 30% lower and consumes 2.2x the power/transistor.

Like
Reply

To view or add a comment, sign in

Explore topics