Infineon Technologies’ Post

New role! Field Application Engineer, Up to $300k OTE! (depending on experience) - #SanFrancisco. Interested? Click the link to apply #ProductManager #sales #SaaS #marketing #presales #TechnologyCareers #TechnologyJobs #software #VRWearables #ProductMarketing #XR #simulationsoftware #IP #VirtualReality #AugmentedReality #EDA #semiconductors #businessdeveloper #AI #Metaverse #salesrecruitment #ICResources #TechnologyRecruitment #electronics #Web3

What's the career path of a “technical architect"? In some cultures career progression requires becoming a manager, which is tricky because not all high performing individual contributors (ICs), have the will and skill to become high performing managers. I’ve discussed the concept of IC career pathing with a few peers recently and from senior engineer to “principle engineer" to “architect" and eventually to “distinguished engineer" there seem to be at least three common sub-tracks, which may blend in different ways: a) Deep Skill So this is like a being a deep domain IC in something like data bases, or AI, distributed systems, an applied skill like prototyping/technical exploration, or solving super hard problems. Examples: At Space X they had one engineer design the landing system until it worked. For iPhone 1.0 they have one developer for each major app--Phone, Music, Browser. Basically this is where one IC can deliver more efficiently and effectively than a team of engineer. b) Field CTO This is an industry authority who speaks at conferences, creates content, educational materials and basically elevates the brand of a company. This may or may not be paired with sales engineering/evangelism/dev rel skillset to also solution on problems with prospects and customers from an architectural level about the company's offerings. Someone like Cassie Kozyrkov comes to mind here from her time at Google. c) Architectural Review Authority This is kind of a "wise OG" role. It’s someone who has the IQ, EQ, history and organizational and architectural context to work with engineering leaders and teams to avoid technical debt, duplication and complexity by reviewing technical proposals and approaches from across a company. Engineering teams focused on specific goals may unintentionally end up over-optimizing for near term or local contexts, while causing company-wide issues. There are probably more sub-tracks and variations. The important thing is ensuring systems are in place to enable each of these functions to perform to their potential.

Get in touch! Field Application Engineer, Up to $300k OTE! (depending on experience) - #SanFrancisco. Want to find out more? Visit our website below #semiconductors #marketing #ProductMarketing #XR #sales #TechnologyCareers #software #EDA #IP #TechnologyJobs #VRWearables #Web3 #simulationsoftware #TechnologyRecruitment #AugmentedReality #Metaverse #salesrecruitment #SaaS #ICResources #electronics #presales #businessdeveloper #ProductManager #AI #VirtualReality

Opportunity

Apply now! Field Application Engineer, Up to $300k OTE! (depending on experience) - #SanFrancisco. Interested? Click the link to apply #TechnologyJobs #marketing #SaaS #Metaverse #businessdeveloper #VRWearables #semiconductors #XR #TechnologyCareers #electronics #ICResources #ProductManager #presales #EDA #ProductMarketing #TechnologyRecruitment #sales #AI #AugmentedReality #Web3 #VirtualReality #salesrecruitment #software #IP #simulationsoftware

#hiring Staff SoC Performance Engineer, Austin, United States, fulltime #opentowork #jobs #jobseekers #careers #Austinjobs #Texasjobs #ITCommunications Apply: https://lnkd.in/gDTuKynm Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC. The collection of silicon proven interconnects, security IP, system controllers, debug and trace and IP tooling are all designed, validated and optimized to be used with Arm Cortex processors and Arm Mali Multimedia IP. Drive the open AMBA interface standard, System IP provides design teams with the foundation for building better systems. Job Description: We are looking for experienced SoC performance engineers who are passionate about enhancing system performance on Arm IPs. This role will involve collaborating with a brilliant team of architects and performance engineers in driving the development of new high-performance interconnect IPs. Your contributions will help in optimizing Arm systems in the infrastructure, automotive, and mobile space. You will apply your performance analysis skills in modeling and evaluating new features for future IPs, and will play a key role in productizing performance models for partners in the Arm ecosystem. Responsibilities: Collaborate with micro-architects and validation engineers to develop cycle-accurate timing models, and drive new feature development for coherent and non-coherent interconnects.Develop a high quality, correlated model for customer evaluation and internal analysis.Work closely with internal and external teams, delivering the collateral needed to develop the highest performing systems based on Arm technology.Validate performance expectations on the IP by designing test suites, identify performance bottlenecks and propose solutions. Required Skills and Experience: Minimum Bachelor's Degree in Electrical Engineering, Computer Engineering or Computer Science with a strong background in computer architecture, microarchitecture, and performance analysis.Minimum of 4 years of experience within the SoC Performance Modeling, RTL in the semiconductor industry.Consistent track record in developing cycle accurate performance models, and evaluating microarchitectural features for performance improvements in future interconnects.Proficient in C for programming for large-scale software development, familiarity with SystemC TLM, and Python scripting language skills. Nice to haves: Knowledge of interconnect micro-architecture design, PCIe and CHI protocols.Understanding of workloads used for performance optimization.Experience with performance verification methodologies, and correlating software models to RTL. In Return: We offer a hybrid approach to home and office working t

Become systems engineering manager in this great organization.

Prediction: Hardware Engineer compensation will go up 📈 Demand for hardware engineers has been steadily on the rise. Numerous companies have mentioned that they’re investing in competitive recruiting strategies for hardware engineering talent, especially with the rise in hardware level AI and GPU based applications. There is an overall deficit in hardware engineer talent. Over time, they’ve become harder and harder to find (ASIC, FFPGA, Processors, SoC, etc). Many of the current professionals are part of an older population that’s starting to retire, with not enough graduates to fill that gap. While compensation has generally been lower for hardware engineers as opposed to their software engineer counterparts, this new influx of demand may change that. It’s still early, but compensation is bound to increase and there are nascent signs of the market starting to heat up. Here are some of the top paying companies for hardware engineers today. These values reflect total comp medians across the role. View more on our leaderboard at: https://lnkd.in/gwkYYutg If you manage compensation for hardware engineers at your company, feel free to send me a note to learn a bit more about the competitive sphere – would appreciate your insight as well! #compensation #hardware #hardwareengineering #salarytransparency

Let’s talk Hardware Engineers. I mentioned this a few weeks ago, and I think we’re going to see more conversations around this as #semiconductormanufacturing continues to return to US soil. “U.S. share of global semiconductor manufacturing capacity has steadily eroded from 37% in 1990 to just 12% in 2020. This is a consequence of the cost of building and operating fabs in the United States relative to that of alternative locations. The ten-year total cost of ownership of a new fab located in the U.S. is 30-50% higher than in competing countries - and 40-70% of this cost is attributable to foreign government incentives.” The good thing is that we have realized this and are working to reverse this trend through new government incentives to build new fabs here in the USA. With all this new construction we will need more engineers that work in these increasingly complex industries to get trained and get working, as Zuhayeer Musa points out there is a definite deficiency in the #HWengineer talent pool and companies are going to face stiff competition to recruit hardware talent in the next decade. I’m here for it! 🤩 Put me in coach! ***I’m seeking a new role in recruiting or sourcing for a company with products that have a HW/SW component.***

Hello Folks, Hope you are doing well! Urgently Hiring Technical Manager – #ChipDesign Back End As a Backend Technical Manager specializing in Semiconductor Chip Design, This role requires a strong technical background in physical design,You will oversee teams engaged in physical design, synthesis, #DFT semiconductor designs. Key Responsibilities: 1. Project Planning and Execution: Develop and maintain project plans, timelines, and milestones for back-end design phases of chip design. 4. Continuous Improvement: Identify opportunities for process improvement and efficiency gains in the chip design workflow. 5. #Synthesis : Oversee the process of Synthesis for correct translation of #RTL to gate-level. . 6.#PhyscialDesign and Optimization: Oversee floor-planning, placement, and routing activities for digital components to optimize for area, power, and performance. 7. Timing Closure and Signal Integrity: Lead Expertise in Static Timing Analysis (#STA) to ensure that the chip meets timing requirements. 8. Clock Tree Synthesis (#CTS) and Power Distribution Network (#PDN):Manage the design and optimization of clock distribution networks. Ensure the robustness and efficiency of the power distribution network by addressing issues such as #IR-Drop/#VoltageDroop. 9. Physical Verification: Oversee physical verification processes, including Design Rule Checking (#DRC) and Layout vs. Schematic (#LVS) checks, Electro-Static Discharge (#ESD) check, and Electrical Rule Check (#ERC). 10. Formal Verification: Oversee Formal Verification(#FV) methods implementation design and reference #RTL. 12.#Multi-#VoltageDesign: Manage designs with multiple voltage domains(multi voltage, power shut down), incorporating and verifying level shifters, isolation and power switch techniques. 13. Hierarchical Desin Integration Coordinate the integration of third-party Intellectual Property (IP) blocks. 14. Tapeout Process: Guide the team through the tapeout process, collaborating with foundries for successful chip fabrication. 16.#EDA Tools for Back End: Expertise in using Electronic Design Automation (EDA) tools specific to back-end design stages. 19. Design for Manufacturing: Oversee Design For Manufacturing(DFM) methods Double-cut-Via, Dummy metal and other #DFM aspects. 20.#DFT : Oversee Design For Test(DFT) methods Memory BIST, Scan, IP test. Incorporating and verifying test circuit preserving the original functionality with comprehensive coverage and minimal overhead. Manage design constraints for #DFT, #ATPG test patterns, Diagnosis. Qualifications: • Masters VLSI design from reputed universities like IIT/NIT with background in Bachelors in Electronics and Communication. • 10 years of experience in the field of semiconductor chip design. interested candidates send resume on [email protected] #vlsidesign #chipdesign #backend #dft #dfm #rtl #drc #sta #pdn #cts #synthesis #semiconductor #physcialdesign #bengaluru #panindia #immediatejoiner #technicalmanager