HuntingCube Recruitment Solutions’ Post

Opportunity

Job opportunity in India

good opportunity

Apply fast

🚀🧠 Calling all tech wizards and engineering superheroes! 💻✨ Are you tired of scrolling through cat memes and dreaming of a job where your brainpower can really shine? Well, dust off your cape because we've got some exciting news! 🦸♂️🦸♀️ 🔍 We're on the lookout for: 🔹 STA Engineer - Whether you can spot a bug from a mile away or you're a pro at untangling those tricky design knots, we want YOU! 🔹 Analog Layout Engineer - If you can turn circuitry into a work of art and have a knack for precision, join us in crafting the future of technology! 🔹 Verification Engineer - Calling all code-crackers and problem-solvers! If you thrive on uncovering the mysteries of digital design, we've got the perfect mission for you! 📍 Locations: Bangalore and Hyderabad - because who says the best jobs are only in Silicon Valley? So, if you've got 4 to 15 years of experience under your utility belt (or even 3 to 8 for our Analog Layout wizards), don't wait! 🚀 Shoot your resume over to [email protected] and let's make some magic together! 💫 #SmartSoC #Engineers #Verification #Analog #Layout #STA #JoinTheSmartSide #TechTalentWanted

Hello Connection, Greetings from TEKFORTUNE IT India Pvt. Ltd! We are #hiring for below #Full_time positions. (Position No: 1) Title: Analog Layout Engineer Experience: 4 10 years  Work Location: Bangalore (onsite) Notice Period: Immediate to 30 Days Max only. (Position No: 2) Title: Analog Mixed Signal Verification Experience: 6 10 years  Work Location: Bangalore (onsite) Notice Period: Immediate to 30 Days Max only. (Position No: 3) Title: Physical Design Engineer Experience: 5 14 years  Work Location: Bangalore (onsite) Notice Period: Immediate to 30 Days Max only. (Position No: 4) Title: Design Verification Engineer Experience: 5 15 years  Work Location: Bangalore (onsite) Notice Period: Immediate to 30 Days Max only. ****Note: Immediate to 30 Days Max only**** If interested, kindly share their CVs at the below mentioned email ID for a quick response. [email protected] / 91-789-838-5987. #fulltime #full_Time #fulltimejobs #hiring #Jobs #JobChange #Job_Change #Opportunity #hiring #Permanent #TechJobs #Bangalore #WFO #Work_from_office #onsite #Engineer #Analog #Semiconductor #AnalogLayoutEngineer #SemiconductorJobs #AnalogDesign #EDA #Exploratory_Data_Analysis #EDAEngineer #HighSpeedSerDes #PowerManagement #Power_Management #Integrated_Circuit #Circuit #ICDesign #VLSIJobs #EngineeringCareers #AnalogMixedSignal #VerificationEngineer #AnalogDesign #CMOS #CMOSDesign #SpiceSimulations #CoSimulation #SystemVerilog #UVM #Universal_Verification_Methodology #VLSIVerification #Very_Large_Scale_Integration #VLSI #PhysicalDesignEngineer #FloorPlanning #PNR #Place_and_Route #STA #Static_timing_analysis #TilePVFixes #SignoffFlows #LeadEngineer #DesignVerification #Ethernet #SOC #System_on_chip #Programming #PERL #ShellScripting #Debugging #Shell_Scripting #USB #Universal_Serial_Bus #HBM #High_Bandwidth_Memory #DDR #Double_Data_Rate #PCIe #Peripheral_Component_Interconnect_Express #HSIOProtocols #CPlusPlus #C #TestBenchDevelopment

🚀🧠 Calling all tech wizards and engineering superheroes! 💻✨ Are you tired of scrolling through cat memes and dreaming of a job where your brainpower can really shine? Well, dust off your cape because we've got some exciting news! 🦸♂️🦸♀️ 🔍 We're on the lookout for: 🔹 STA Engineer - Whether you can spot a bug from a mile away or you're a pro at untangling those tricky design knots, we want YOU! 🔹 Analog Layout Engineer - If you can turn circuitry into a work of art and have a knack for precision, join us in crafting the future of technology! 🔹 Verification Engineer - Calling all code-crackers and problem-solvers! If you thrive on uncovering the mysteries of digital design, we've got the perfect mission for you! 📍 Locations: Bangalore and Hyderabad - because who says the best jobs are only in Silicon Valley? So, if you've got 4 to 15 years of experience under your utility belt (or even 3 to 8 for our Analog Layout wizards), don't wait! 🚀 Shoot your resume over to [email protected] and let's make some magic together! 💫 #SmartSoC #Engineers #Verification #Analog #Layout #STA #JoinTheSmartSide #TechTalentWanted

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/gWBN_KmC Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/eU9XYT9H Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.