We're #hiring a new Software Simulation Engineer (Clearance) in Virginia. Apply today or share this post with your network.
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Do you have a background in radar? If so this week's hot jobs in Greater London are: SYSTEMS ENGINEER SENIOR SYSTEMS ENGINEER PRINCIPAL FPGA DESIGN ENGINEER SENIOR EMBEDDED SOFTWARE ENGINEER SENIOR PRINCIPLE RADAR ENGINEER Please feel free to contact me [email protected] or share with your network. #radar #systems #engineer #FPGA #embedded #software
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-Wait a minute, Doc. Ah... Are you telling me that you built a Radar SoC... in a DeLorean? -The way I see it, if you're gonna build a Radar SoC into a car, why not do it with some style? -Ok Doc,but we better back up. We don't have enough road to get up to 88Mph. -Roads? Where we're going, we don't need roads. Bosch to the future 🚗 🔥 🔥 🔥 Do you want to be part of the future of automotive electronics? we have an open position, we are looking for a Senior Mixed Signal Verification Engineer. If you are interested please visit https://lnkd.in/d_EsabWQ and submit your CV. P.S. Thanks to all of you that interact and share my funny posts 😄. Any help is usefull to reach good candidates. This time my manager Miguel Chanca Martin promise me a bonus if a reach a good number of interactions and reactions, so please help me and also help your network to find a very good job in a very good place. Miguel how many reactions for the bonus? 🤣 P.S.2 Some colleagues properly pointed me that I´m losing young people and not reaching GenZ wit my posts. I promise to solve this in my next post, maybe a Frozen based post is a good option 🤣 #LikeABosch #Bosch #hiring #work
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🚀 Excited to share a comprehensive functional verification video course that dives deep into essential verification concepts and tools! Whether you're a beginner or looking to refine your skills, this course covers it all: - Understanding Verification & Testbenches - Approaches & Strategies in Functional Verification - Tools & Techniques including Linting, Simulators, Models, Code Coverage - Key Practices for Writing and Architecting Testbenches, Simulation Management, and more - Efficiency Tips to reduce work in verification Perfect for those in the VLSI and semiconductor industries looking to boost their verification expertise. 🛠️💡 Check it out for a detailed journey through the verification landscape! ➡️ Contact to book - https://lnkd.in/gVpirNhG #Verification #Testbenches #FunctionalVerification #VLSI #Semiconductor
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🚀 Embarking on my verification journey with the completion of the "SOC Verification using SystemVerilog" course! 🎓 Key takeaways: - Understanding SoC/ASIC/VLSI design verification flow - Mastering SystemVerilog for functional verification - Hands-on experience in coding, simulating, and verifying SystemVerilog testbenches. One of the project was Design and Verification of a 2x2 Ethernet Switch, honing skills in: - Coding exercise to build the design to be verified - Coding interfaces and clocking blocks to connect - Building class-based testbench components - Connecting all testbench components using mailboxes - Building the top testbench with DUT, compile and simulate Up next, gearing up for the Advanced UVM workshop. This marks the inception of an exciting verification journey! 💡 #VerificationMilestone #UVMWorkshopAhead #ContinuousGrowth
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Supercharging Design Verification Success | Empowering you with UVM, Linux, AMBA Protocols, and SystemVerilog | Let's connect and fuel our learning journey! Follow for valuable insights and growth opportunities.
Layered architecture is a design pattern that divides the verification environment into multiple layers, each with a specific function and responsibility. This helps to create a modular, reusable and scalable verification code that can be easily maintained and debugged. Some of the common layers in a verification environment are: - Test layer: This layer contains the test scenarios and sequences that generate stimulus for the design under test (DUT). - Environment layer: This layer contains the components that interact with the DUT, such as drivers, monitors, checkers, scoreboards and coverage collectors. - Configuration layer: This layer contains the parameters and settings that control the behavior and functionality of the environment components. - Utility layer: This layer contains the common functions and methods that are used by the other layers, such as logging, reporting, randomization and synchronization. By using layered architecture, verification engineers can achieve better code quality, readability and reusability, as well as faster verification cycles and higher coverage. Crash course in verification! Fast-track your career with practical SystemVerilog training: https://lnkd.in/gTWbpPGx #careergoals #systemverilog #verification
Empower Your Verification Skills with GrowDV - Your Ultimate Learning Partner
growdv.com
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Hai all, I'm excited to share the latest project I've been working on: GCD (Greatest Common Divisor) Design and Verification in SystemVerilog! 🚀 In this project, I had the opportunity to design and verify a robust GCD algorithm using SystemVerilog, and I was responsible for creating essential components including: 🔹 Testbench Generator: Developed a versatile testbench generator for automated test case generation, allowing for comprehensive verification scenarios. 🔹 Driver: Designed a robust driver module to stimulate the GCD algorithm with a wide range of inputs, ensuring rigorous testing. 🔹 Monitor: Implemented a sophisticated monitor to continuously track and record GCD computation results, facilitating real-time analysis. 🔹 Scoreboard: Constructed an efficient scoreboard to compare GCD outputs against golden reference values, ensuring functional correctness. These components played a crucial role in achieving a high level of verification confidence in our GCD design. Key highlights of the project: 🔹 SystemVerilog RTL design of the GCD algorithm. 🔹 Development of comprehensive testbenches and stimulus generation. 🔹 Simulation and verification using EDA Playground tool. 🔹 Achieving functional correctness and performance optimization. I'm proud to say that the project was a success, and it was an excellent opportunity to apply my skills in digital design and verification. Thank you all. #SystemVerilog #DigitalDesign #Verification #GCD
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🚀 Let's Dive into Verification!! 🚀 🤔 What is the difference between a reg, wire and logic data type in SystemVerilog? #vlsi #verification #semiconductors #verilog #systemverilog #asic #electronics #designverification #interviewpreparation #staytuned 📚
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