Special Report: Partitioning In The Chiplet Era https://lnkd.in/g8AwN9gC Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs. By Ann Mutschler. #chiplets #partitioning #EDA #semiconductor Arif Khan Cadence Design Systems Letizia Giuliano Alphawave Semi Tim Kogel Synopsys Inc Ashley Stevens Arteris David Fritz Siemens EDA (Siemens Digital Industries Software) Eliyan Corporation Kevin Donnelly Ashraf Takla Mixel, Inc. Robert Dimond Arm Mayank Bhatnagar Chun-Ting "Tim" Wang Lee, PhD Keysight Technologies Elad Alon Blue Cheetah Analog Design, Inc.
Semiconductor Engineering
Online Audio and Video Media
Silicon Valley, CA 86,497 followers
Deep insights for the tech industry
About us
Semiconductor Engineering was created by chip architects, engineers, journalists, end users, industry organizations and standards bodies to provide deep insights into the increasingly complex task of designing, testing, verifying, integrating and manufacturing semiconductors, as well as insights into the market dynamics that make it all possible. The goal of this site is to provide useful, independently developed content through targeted monthly newsletters, weekly updates, timely news alerts, videos, independent research, and a portal that serves as a forum for exchanging ideas and answering questions.
- Website
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http://semiengineering.com
External link for Semiconductor Engineering
- Industry
- Online Audio and Video Media
- Company size
- 2-10 employees
- Headquarters
- Silicon Valley, CA
- Type
- Self-Owned
- Founded
- 2013
Locations
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Primary
Silicon Valley, CA, US
Employees at Semiconductor Engineering
Updates
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Perfection sometimes stands in the way of progress, and there is evidence this may be happening with chiplets. It may be time to slow down and make real progress. Final in 3 part series with 5 experts. By Brian Bailey. With Elad Alon, CEO of Blue Cheetah Analog Design, Inc.; Mark Kuemerle, vice president of technology at Marvell Technology; Kevin Yee, senior director of IP and ecosystem marketing at Samsung Electronics; Sailesh Kumar, CEO of Baya Systems; and Tanuja Rao, executive director, business development at Synopsys Inc. https://lnkd.in/gXPaYJgU #chiplets #semiconductor #advancedpackaging
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Creating complex multi-chiplet systems is no longer a back-of-the-envelope diagram, but viable methodologies are still in short supply. By Brian Bailey. https://lnkd.in/gDTE36hr #EDA #virtualprototyping #digitaltwins #verification Neil Hand Marc Serughetti Chris Mueth Roland Jancke Fraunhofer IIS, Division Engineering of Adaptive Systems EAS Siemens Digital Industries Software Synopsys Inc Keysight Technologies
Pressure Builds To Adopt Virtual Prototypes
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Many EDA companies have taken the first steps to incorporate generative AI into their tools, and in such tightly controlled environments GenAI appears to have great benefits. But its broader adoption has been delayed by its notorious inaccuracy, giving results that are often out of date, untrue, and unsourced. That’s starting to change. By Karen Heyman. https://lnkd.in/gNWrsxpk #RAG #EDA #semiconductor #GenAI #RAFT Dan Yu The AI Alliance Stanford University Rob Knoth Siemens Digital Industries Software Perplexity Patrick Lewis Hugging Face Amanda Saunders NVIDIA Cadence Design Systems Microsoft Explainpaper Elik Eizenberg Scroll EnCharge AI Alphawave Semi Tony Chan Carusone Dean Wampler
RAG-Enabled AI Stops Hallucinations, Adds Sources
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SemiEngineering's latest Test, Measurement & Analytics Newsletter https://lnkd.in/gV9WtN4k #semiconductor #semiconductortest #waferdefects #paralleltest #AMS PDF Solutions Nordson TEST & INSPECTION proteanTecs Advantest Onto Innovation Synopsys Inc Bruker Nano Surfaces & Metrology DR YIELD Teradyne Siemens Digital Industries Software NI (National Instruments)
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New technical papers recently added to Semiconductor Engineering’s library https://lnkd.in/gyKa9GpC #semiconductor #PIM #CNFETs #STTMRAM #AI #GAAFETs #NBTI Korea Advanced Institute of Science and Technology Dongjae Lee, Bongjoon Hyun, Minsoo Rhu Chih-Yu (Andrew) Lai, Tathagata Srimani, Max Shulaker Stanford University Carnegie Mellon University Analog Devices Semiconductor Industry Association UC Santa Barbara HP Labs & Ventures Forschungszentrum Jülich RWTH Aachen University Tinish Bhattacharya Giacomo Pedretti Thomas Van Vaerenbergh CEA-Leti Université Grenoble Alpes, CNRS SPINTEC Nathan Roussel Olivier Potin Gregory DI PENDINA Jean-Max Dutertre Jean-Baptiste Rigaud Georgia Institute of Technology University of California, Berkeley IBM Research Zishen Wan Che-Kai Liu Hanchen Yang Ritik Raj Hanyang University Alsemy
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Chip Industry Week In Review https://lnkd.in/dKy9Muc5 Google’s AlphaChip; 300mm fab equip spending; TSMC-EDA partnerships; $123M CHIPS Act; CXL memory standards; MIPI’s A-PHY v2.0; 12-stack HBM3E; LLMs for chip design and manufacturing; CHIPS Metrology research access; Workforce Center of Excellence and more. #semiconductor #semiconductormanufacturing #EDA SEMI Natcast.org TSMC Ansys Siemens Digital Industries Software Synopsys Inc Cadence Design Systems Intel Corporation Polar Semiconductor SK hynix Google DeepMind Tata Group POWERCHIP SEMICONDUCTOR (INDIA) PRIVATE LIMITED Anna Goldie CHIPS for America Semiconductor Industry Association Ephos Ampere Micron Technology NVIDIA Munters ZutaCore National Institute of Standards and Technology (NIST) Missouri University of Science and Technology Defense Advanced Research Projects Agency (DARPA) Canon Inc. Alphawave Semi Arm Meta Infineon Technologies Preferred Networks, Inc. Fermilab Oak Ridge National Laboratory Stephen Jesse Argonne National Laboratory Justin Connell Mohammad Eslami Chun-Wei Chiu David Borrok Andrew Sarangan
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Special Report: Using AI To Glue Disparate IC Ecosystem Data https://lnkd.in/gCMtsnSy Why the chip industry is so focused on large language models for designing and manufacturing chips, and what problems need to be solved to realize those plans. By Ed Sperling and Ann Mutschler. #EDA #AI #LLMs #semiconductor #chipdesign Stelios Diamantidis Synopsys Inc Ira Leventhal Advantest Tignis Nitza Basoco Teradyne Kunle Olukotun SambaNova Systems John Kibarian PDF Solutions Keysight Technologies Chris Mueth Jon Herlocker Mike EllowSiemens Digital Industries Software Eliyan Corporation Patrick Soheili Rob Knoth Cadence Design Systems Steve Roddy Quadric Patrick Donnelly Expedera Inc. Rob Aitken Ravi Subramanian
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Controlling interference in today’s SoCs and advanced packaging requires a combination of innovative techniques, but new challenges emerge. By Gregory Haley. https://lnkd.in/gvz3gbeh #EMI #semiconductor #RF #AMS Jian Yang Dick Otte Myungwoon (brian) Hwang Heidi Barnes Amkor Technology, Inc. Synopsys Inc Promex Industries Inc. Keysight Technologies
Managing EMI in High-Density Integration
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Optimizing Wafer Edge Processes For Chip Stacking https://lnkd.in/gVsxzkse Several critical processes address wafer flatness, wafer edge defects and what’s needed to enable bonded wafer stacks. By Laura Peters. #semiconductor #advancedpackaging #chiplets #3DNAND #HBM #waferdefects #CMP #etch #edgedeposition Alex Smith Brewer Science Kenneth Larsen Synopsys Inc Ian Latchford Lam Research Boyd F. Tignis Michel Walden TECHCET and the Critical Materials Council Applied Materials Ebara Technologies Axus Technology Sally Ann Henry ACM RESEARCH, INC. CEA-Leti Shaun Bowers EV Group Thomas Uhrmann