Nidhi G.

Nidhi G.

Nainital, Uttarakhand, India
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Jayoti Vidyapeeth Women's University, Jaipur, Rajasthan, India

About

Hello everyone,
Welcome to my profile! My name is Nidhi Gopal.
E-mail is…

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Activity

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Experience

  • Aryabhatta Research Institute of Observational Sciences Graphic

    Aryabhatta Research Institute of Observational Sciences

    Nainital, Uttarakhand, India

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    Noida, Uttar Pradesh, India

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    Noida, Uttar Pradesh, India

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    India

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    New Delhi, Delhi, India

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    Jaipur, Rajasthan, India

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    Chandigarh Area, India

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    Roorkee Area, Uttarakhand

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    Haridwar Area, Uttarakhand, India

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    Bangalore , Karnataka , India

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    Pune Area, Maharashtra, India

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    Aurangabad Area, Maharashtra, India

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    Haridwar Area, India

Education

  • Jayoti Vidyapeeth Women's University, Jaipur, Rajasthan, India

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    Activities and Societies: Served as E(Entreprenuership-Leader) National Entrepreneurship Network(NEN) , Jaipur, Rajasthan, India.

    Dissertation Project: PLC Automation using VHDL Programming.
    Language: VHDL [VHSIC Hardware Descriptive Language]
    Software Tools: Xilinx ISE Design Suite.
    Summary: In this dissertation work, study of CNC (Computer Numerical Control) Machines, PLC(Programmable Logic Controller) Programming using VHDL Language is designed and simulated and challenges, design aspects and application areas of VHDL in CNC Machines have been discussed.

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    Completed Advanced VLSI Design and Verification Course from March 2015- August 2015, which had included work upon projects :

    1. Router 1X3 - RTL Design and Verification.

    Brief Description:
    • Architected the design (Top-Level Architecture); Implemented the RTL using Verilog HDL and using System Verilog.
    • Verified the RTL module using System Verilog, generated functional and code coverage for the RTL verification sign-off, Synthesized the design & Checked Coverage through…

    Completed Advanced VLSI Design and Verification Course from March 2015- August 2015, which had included work upon projects :

    1. Router 1X3 - RTL Design and Verification.

    Brief Description:
    • Architected the design (Top-Level Architecture); Implemented the RTL using Verilog HDL and using System Verilog.
    • Verified the RTL module using System Verilog, generated functional and code coverage for the RTL verification sign-off, Synthesized the design & Checked Coverage through Questasim Coverage Report.

    2. Serial Peripheral Interface- Controller Core- Verification

    Brief Description:
    Architected the class based verification environment in UVM (Written Testbench from the scratch) using System Verilog & Verified the RTL module using System Verilog & Generated functional and code coverage for the RTL verification sign-off & Verified Coverage through Questasim Coverage Report .

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    Activities and Societies: National Entrepreneurship Network, Jayoti Utsav etc

    B.Tech in Electronics and Communication Engineering with 76.16% .
    --​> Projects Worked on:
    1. Image Analysis using Wavelet Transformation.
    2. Wireless Instrumentation and Networking in Turbines and Generators.
    3. Designing & Programming of a Robot using PIC(Programmable Interface Controller) Microcontroller.

    --​>Industrial Visits during B.Tech:
    1. 15 Days industrial exposure of BSNL(Bharat Sanchar Nigam Limited), Haridwar.
    2. Industrial Visit at Omega Electronics,…

    B.Tech in Electronics and Communication Engineering with 76.16% .
    --​> Projects Worked on:
    1. Image Analysis using Wavelet Transformation.
    2. Wireless Instrumentation and Networking in Turbines and Generators.
    3. Designing & Programming of a Robot using PIC(Programmable Interface Controller) Microcontroller.

    --​>Industrial Visits during B.Tech:
    1. 15 Days industrial exposure of BSNL(Bharat Sanchar Nigam Limited), Haridwar.
    2. Industrial Visit at Omega Electronics, Jaipur.
    3. Industrial Visit at Infosys BPO(Business Process Outsourcing), Jaipur.
    4. Industrial Visit at BEL(Bharat Electronics Limited), Kotdwar.

    --​>Workshops:
    Workshop of Advance Soft Computing Techniques using MATLAB in National Institute of Hydrology(NIH), Roorkee.

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    Activities and Societies: Annual Function of Shivedale School, Haridwar, National Science Olympiad, National Cyber Olympiad, HOPE, HELPAGE INDIA

    --> Headgirl of my school in 2009, and House Captain too, used to design notice boards, recite news in morning assembly, deliver speeches , participated in debate competitions and participated in various dance and play activities in annual function of my school.
    --> Certificate of Appreciation by Help-Age India for Social Service.
    --> Certificate of Appreciation by HOPE(Home for Orphan, Poor and Education).
    --> Certificate of Merit in 1st Uttaranchal State Sub Junior…

    --> Headgirl of my school in 2009, and House Captain too, used to design notice boards, recite news in morning assembly, deliver speeches , participated in debate competitions and participated in various dance and play activities in annual function of my school.
    --> Certificate of Appreciation by Help-Age India for Social Service.
    --> Certificate of Appreciation by HOPE(Home for Orphan, Poor and Education).
    --> Certificate of Merit in 1st Uttaranchal State Sub Junior Basketball Championship.
    --> Certificate of Honor in "Interhouse Basketball Tournament", and a member of winning team in 2004.
    --> Certificate of Participation in Arty Painting Contest.
    --> Obtained City Rank:16 in 6th National Science Olympiad, in 2003.
    --> Obtained School Rank: 2, City Rank: 2 and State Rank: 92 in 4th National Cyber Olympiad, in 2004.

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    Activities and Societies: Participated in various Dance and Play Competitions in annual function of my school, HOPE, HELPAGE INDIA.

    Member of School club and in addition to that I have Scored 98/100 in Social Science in 10th.

Licenses & Certifications

Volunteer Experience

  • National Entrepreneurship Network Graphic

    E-Leader(Entrepreneurship Leader)

    National Entrepreneurship Network

    - 1 year 1 month

    Social Services

    Entrepreneurship Leader of Jayoti Vidyapeeth Women's University, Jaipur, Rajasthan, India, participated in National Entrepreneurship Network, Jaipur, and represented my university in Jaipur.

  • HelpAge India Graphic

    Student Volunteer

    HelpAge India

    - 1 month

    Social Services

    Certificate of Appreciation in Social Service by HelpAge India in 2003.

  • Student Volunteer

    HOPE India

    - 2 months

    Social Services

    Certificate of Appreciation from HOPE(Home for Orphan Poor and Education) in 2005-2006.

  • IEEE Graphic

    Reviewer

    IEEE

    - Present 4 years 3 months

    Science and Technology

    Reviewed many Research Papers Published in IEEE and obtained reviewer recognition certification.

  • Blood donor in blood bank

    Maa Gange Blood centre, Haridwar

    - Present 7 months

    Social Services

    I've donated blood in a nearby blood centre, e.g. Maa Gange Blood centre,Haridwar, Uttarakhand,India

  • Volunteer

    Rashtriya Charitable Blood Centre

    - 1 month

    Health

    I have donated blood in a national level blood center-located at Noida, Uttar Pradesh- Volunteered as a blood donor- Rashtriya Charitable Blood Centre,Hoshiyarpur,Noida,Uttar Pradesh,India.

Publications

  • Place & Route Optimization of OpenMSP430 Microcontroller using Verilog

    International Journal of Engineering , Science and Computing (Impact Factor- 5.611)

    Placement and Routing are the two most important steps of physical design in VLSI Backend. Placement is an essential step in Electronic Design Automation (EDA) – it is the portion of physical design flow that assigns exact locations for various circuit components within the chip’s core area. It determines the necessary wiring, while respecting the constraints and optimizing routing objectives. Routing, on the other hand, is the technique of locating a set of wires in the routing space that…

    Placement and Routing are the two most important steps of physical design in VLSI Backend. Placement is an essential step in Electronic Design Automation (EDA) – it is the portion of physical design flow that assigns exact locations for various circuit components within the chip’s core area. It determines the necessary wiring, while respecting the constraints and optimizing routing objectives. Routing, on the other hand, is the technique of locating a set of wires in the routing space that connect all the nets in the netlist. The capacities of channels, width of wires and wire crossings often need to be taken into consideration. In this paper, Place and Route Optimization of a microcontroller architecture of openMSP430 using Qflow tool is done, placement results were observed using Graywolf and qrouter , and , by implementing the Verilog files of the different modules.

    See publication

  • Router 1X3 - RTL Design and Verification

    International Journal of Innovative Research , Science and Engineering and Technology (Impact Factor-4.371)

    Routing is a process to move a packet of data from source to destination, and router is a networking device that forwards data packets between computer networks. This paper, mainly emphasizes upon the study of router device, it's top-level architecture, and how various sub modules of router, i.e. Register, FSM, FIFO and Synchronizer are synthesized, simulated and finally connected to its top module.

    See publication

  • Router 1X3-RTL Design and Verification

    World Academy of Science , Engineering and Technology Dubai U.A.E.

    This paper is published in the conference proceedings also.

    See publication

  • SPI Controller Core - Verification

    SSRG International Journal of VLSI and Signal Processing

    This paper mainly deals with Serial Peripheral Interface and logical Implementation through RTL, Synthesis and Simulation by making Test benches of various modules involved using Universal Verification methodology, it is done with the help of Questasim 10.0b software.

    See publication

  • Application of Wireless Instrumentation in heavy power plant

    International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering(Impact Factor-5.621)

    This paper deals with the idea of implementation of wireless technology in Heavy Equipment Power Plant. Wireless technology being the modern and fastest results in lower installation time and lower installation costs, proves to be an asset over wired one in many aspects of engineering.

    See publication

  • PLC Automation using VHDL Programming

    International Journal of Science Engineering and Technology

    Research paper in MTech level, carried out with HOD (Head of Department) of Jayoti Vidyapeeth Women's University, Jaipur, and Senior Manager of BHEL Haridwar, which included research study of PLC Automation using VHDL Programming. PLC Programming is widely used in CNC Machines of Heavy Power plants. This research paper included concern about how VHDL Programming can be inculcated for CNC Machines and its benefits and scope in future.

    See publication

  • Image Compression Technique using Wavelet Transformation

    International Journal of Science, Engineering and Technology

    Research Paper, which included study about Digital Image Processing. Wavelet Transforms are used for multi resolution image compression at pixel level. This paper explores  the use of current wavelet algorithm and programming for multi resolution image compression. The  aim is to investigate how appropriate these wavelet transform algorithms are for compression and  analysis of an image. 

    See publication

  • VHDL Implementation for FSM based approach of Traffic Light Controller

    International Journal of Science, Engineering & Technology

    Research paper in an International Journal which included study about how VHDL language can be implemented in traffic light controller. FSM Based approach for traffic light controller is taken into the view.

    See publication

  • Taur’s Model: An Analytical Solution for Drain Current in Undoped body SDG MOSFET

    International Journal of Science Engineering and Technology(Impact Factor-3.632)

    This paper presents a long channel drain current model for undoped SDG MOSFET which is based on Taur’s approach. The model is derived rigorously from the exact solution to Poisson’s and current continuity equation without the charge‐sheet approximation. The model involves implicit functions, iterations are required to solve the equations. It is shown that the results of the analytic model exhibit excellent agreement with two‐dimensional (2‐D) numerical simulation values, and yet, the…

    This paper presents a long channel drain current model for undoped SDG MOSFET which is based on Taur’s approach. The model is derived rigorously from the exact solution to Poisson’s and current continuity equation without the charge‐sheet approximation. The model involves implicit functions, iterations are required to solve the equations. It is shown that the results of the analytic model exhibit excellent agreement with two‐dimensional (2‐D) numerical simulation values, and yet, the expressions are continuous in all operation regions. Finally, the implementation in Matlab 7.5 is discussed to investigate the results.
    Index Terms: Symmetric Double‐Gate, Drain–Current Model, Undoped Body.

    See publication

Courses

  • ASP.NET C#

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  • IBM Certified Python programming Training Course

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  • IEEE Short Course on Energy 4.0: BigData IOT and Smartgrid

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  • Introduction to Software Testing and Automation by The university of Minnesota, U.S.A-Online collaboration with CourseEra.

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  • Microsoft Azure : Microsoft Security Compliance and Identity Fundamentals

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  • VLSI-RN

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Projects

  • SPI Controller Core - Verification

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    SPI controller design and verification through UVM on Questasim software.
    -> HVL: System Verilog
    -> TB Methodology: UVM
    -> EDA Tools: Questasim 10.0b

    -->Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves.

    --> Responsibilities:
    1. Architected the class based verification environment in UVM.
    2. Verified the RTL module…

    SPI controller design and verification through UVM on Questasim software.
    -> HVL: System Verilog
    -> TB Methodology: UVM
    -> EDA Tools: Questasim 10.0b

    -->Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves.

    --> Responsibilities:
    1. Architected the class based verification environment in UVM.
    2. Verified the RTL module using System Verilog.
    3. Generated functional and code coverage for the RTL verification sign-off.

    Other creators

  • Router 1X3 - RTL Design and Verification

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    -> HDL: Verilog
    -> HVL: System Verilog
    -> TB Methodology: UVM
    -> EDA Tools: Questasim and ISE

    --> Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

    --> Responsibilities:
    1. Architected the design(Top-Level Architecture).
    2. Implemented RTL using Verilog HDL.
    3. Architected the class based verification environment using system Verilog.
    4.…

    -> HDL: Verilog
    -> HVL: System Verilog
    -> TB Methodology: UVM
    -> EDA Tools: Questasim and ISE

    --> Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

    --> Responsibilities:
    1. Architected the design(Top-Level Architecture).
    2. Implemented RTL using Verilog HDL.
    3. Architected the class based verification environment using system Verilog.
    4. Verified the RTL model using SystemVerilog.
    5. Generated functional and code coverage for the RTL verification sign-off.
    6. Synthesized the design.
    7. Checked Coverage through Questasim Coverage Report.

    Other creators

  • Image Compression Technique Using Wavelet Transformation

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    -> Languages used: MATLAB
    -> Tools used: MATLAB R2008a.

    --> Description: Major project of B.Tech 4th year, carried out at IRDE, DRDO, Dehradun, Uttarakhand, which included study about Wavelet theory, image compression and its application in defence organizations.

    -->Responsibilities:
    1.Generated MATLAB program.
    2.Observed output by Haar transformation at various levels of decomposition.

    Other creators

  • PLC Automation using VHDL Programming

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    ->Language: VHDL
    ->Tools Used: Xilinx ISE

    -->Description: Six months Dissertation work of MTech Final Year , which included research study about CNC Machines, PLC Programming of CNC Machines in heavy power plant and how VHDL Language can be implemented in CNC Machines, and its benefits and scope in an industry.

    --> Responsibilities:
    1. Interaction with training coordinator and discussion about VHDL Implementation in a heavy power plant.
    2. Learning about PLC…

    ->Language: VHDL
    ->Tools Used: Xilinx ISE

    -->Description: Six months Dissertation work of MTech Final Year , which included research study about CNC Machines, PLC Programming of CNC Machines in heavy power plant and how VHDL Language can be implemented in CNC Machines, and its benefits and scope in an industry.

    --> Responsibilities:
    1. Interaction with training coordinator and discussion about VHDL Implementation in a heavy power plant.
    2. Learning about PLC Automation.

    Other creators

  • Wireless Networks employed with DCS of Turbines/Generators.

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    -> Protocols Used: Wireless HART and ISA 100.11
    -> Tools Used : Smart Wireless Gateway

    -->Description: Industrial Training of B.Tech 3rd year, carried out at BHEL, Haridwar, Uttarakhand, which included study about Wireless instrumentation and Networking in turbines/generators in a Heavy Power Plant. Learnt about Control Logic Implementation and Instrumentation through Wireless Devices in Heavy Power Plant.

    -->Responsibilities:
    1.Interaction with training…

    -> Protocols Used: Wireless HART and ISA 100.11
    -> Tools Used : Smart Wireless Gateway

    -->Description: Industrial Training of B.Tech 3rd year, carried out at BHEL, Haridwar, Uttarakhand, which included study about Wireless instrumentation and Networking in turbines/generators in a Heavy Power Plant. Learnt about Control Logic Implementation and Instrumentation through Wireless Devices in Heavy Power Plant.

    -->Responsibilities:
    1.Interaction with training coordinator regarding how things work in an industry.
    2.Learning about various auxiliary systems attached with turbines/generators.
    3.Gathering first hand information from trainer and data collection from control room.
    4. Compiling all results and findings of the project.

  • Robologics Certification

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    Designed and Programmed a robot, using MPLAB IDE software and PIC Mcrocontroller.
    ->Tools:Microchip MPLAB IDE.

    -->Description: Short-term Project in B.Tech 2nd year, carried out by Purpleleap, Bangalore in my university, which included designing and programming of a small robot.

    -->Responsibilities:
    1.Assembling all parts of a small Robot.
    2.Programming of operations of Robot.
    3.Observing all the operations like pit detection, wall…

    Designed and Programmed a robot, using MPLAB IDE software and PIC Mcrocontroller.
    ->Tools:Microchip MPLAB IDE.

    -->Description: Short-term Project in B.Tech 2nd year, carried out by Purpleleap, Bangalore in my university, which included designing and programming of a small robot.

    -->Responsibilities:
    1.Assembling all parts of a small Robot.
    2.Programming of operations of Robot.
    3.Observing all the operations like pit detection, wall following, line following etc by a robot.

Honors & Awards

  • Awarded for blood donation as a volunteership work in Noida, Uttar Pradesh,India

    Rashtriya Charitable Blood Centre

    I've donated blood as a blood donor and obtained an award from Rashtriya Charitable Blood Centre,Noida, Uttar Pradesh,India.

  • Certificate of Reviewer Recognition by IEEE

    IEEE

  • Certificate of participation on Google Earth tools for education

    TERI SAS

    Learnt about google earth tool in education.

  • Certificate of participation on Online National Awareness Workshop on UGC DAE CSR Facilities

    UGC-DAE CSR and HNB Garhwal University

  • Accepted for Paper Presentation in an International Conference

    ICICCT 2016(International Conference on Information, Communication and Computing Technology), New Delhi

  • Oral Presenter Delegate

    World Academy of Science, Engineering and Technology, Dubai, UAE

    Accepted and Invited for ICECS (18th International Conference on Electronics and Communication Systems) 2016 to present a research paper , as a "Oral Presenter Delegate".

  • Certification of creating an ecosystem of Entrepreneurship by serving as E-Leader(Entrepreneurship Leader)

    National Entrepreneurship Network, Jaipur

  • First prize in Kathak Dance from Bhathkhande Sangeet Mahavidyalaya, Haridwar

    Bhathkhande Sangeet Mahavidyalaya, Haridwar

  • Certificate of Appreciation from HOPE (Home for Orphan Poor & Education)

    HOPE

  • Certificate of Merit in 1st Uttaranchal State Sub-Junior Basketball Championship

    Omkarananda Saraswati Nilayam, Rishikesh, Uttarakhand

  • Certification of Participation in 5th Aspen Crew Junior Basketball Championship

    District Basketball Association, Dehradun, Uttarakhand.

  • Senior Diploma in Kathak Dance from Prayag Sangeet Samiti, Allahabad

    Prayag Sangeet Samiti , Allahabad

  • Certificate of Appreciation in Social Service by Help-Age India

    Help-Age India

  • First Prize from Madhurima Sangeet Samiti, Haridwar in Kathak Dance

    Madhurima Sangeet Samiti, Haridwar

    Won first prize in Kathak Dance Competition , and received award from Shri Bal krishna for kathak dance.

  • Junior Diploma in Kathak Dance from Prayag Sangeet Samiti , Allahabad

    Prayag Sangeet Samiti, Allahabad

Test Scores

  • Versant English Test

    Score: 60 out of 80

  • Dissertation Presentation of M.Tech on "PLC Automation using VHDL Programming"

    Score: 154/200

    Scored 77% in Presentation of Dissertation presentation on PLC Automation using VHDL Programming (MTech Final Year).

  • Project Presentation of Image Compression Technique using Wavelet Transformation(Major Project of B.Tech)

    Score: 178/200

    Scored 89% in Presentation of Image Compression Technique using Wavelet Transformation(Major Project of B.Tech)

  • VLSI Physical Design

    Score: 83/100

    I’ve scored 83/100 in 11th trimester in the subject of "VLSI Physical Design".

  • Analog and Mixed Signal IC's

    Score: 85/100

    I’ve scored 85/100 in 10th Trimester in subject of "Analog and Mixed Signal IC's".

  • CMOS VLSI Design

    Score: 84/100

    I’ve scored 84/100 in 10th Trimester in subject of "CMOS VLSI Design".

  • Embedded Systems

    Score: 85/100

    I’ve scored 85/100 in 10th trimester in subject of "Embedded Systems".

  • Industrial Training and Presentation

    Score: 168/200

    I’ve scored 84% in industrial training and presentation of summer internship.

  • CBSE 10th Board Exam

    Score: 98/100

    I’ve scored 98/100 in Social Science in 10th Board Exam.

Languages

  • English

    Full professional proficiency

  • Hindi

    Full professional proficiency

Organizations

  • HELPAGE India

    Volunteer

    - Present

  • Maven Silicon Softech Pvt Ltd, Bangalore

    Trainee

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  • Instruments Research and Development Organization, DRDO, Dehradun

    Major Project Trainee

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    Project in BTech Final year, upon Image Analysis using Wavelet Transformation using MATLAB.

  • TOPS Technologies Private Limited, Dehradun

    ASP.NET Student

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    Learnt ASP.NET and made an online food restaurant website with the help of ASP.NET4.0 & C#.

  • Jayoti Vidyapeeth Women's University, Jaipur

    BTech MTech Student

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  • National Institute of Hydrology , Roorkee

    Workshop Trainee

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    Workshop attended and learnt about various features of MATLAB used in Hydrological Modelling Techniques.

  • BHEL, Haridwar

    Summer Trainee

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  • HOPE India

    Volunteer

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