Chandra Sekhar Mallela

Chandra Sekhar Mallela

Bengaluru, Karnataka, India
9K followers 500 connections

Activity

Licenses & Certifications

Volunteer Experience

  • Mathematics Teacher

    Voluntary

    - Present 12 years 10 months

    Education

    I enjoy teaching Mathematics to the kids focusing on their stumbling blocks. Taught mathematics till Engineering level.

Publications

  • Hardware Logic Implementation of High-Throughput Configurable-CRC Computation Using Data Folding Technique

    DTTC 2022

    The data folding CRC computation technique demonstrates a clear improvement in the levels of logic through parallelization, which is inevitable for the cutting-edge high-throughput applications. The results show a highly scalable model for high throughput systems ranging from 256Gbps to 2Tbps (intuitively, the technique can sustain the lower levels of logic even for systems with more than 2Tbps throughput).

    Other authors
  • DTF implementation and quantitative analysis of burst window for SoCs requiring low pin-count and debug capture at speed

    DTTC 2021

    The VISA (Visualization of Internal Signal Architecture) based post-silicon debug architecture, implemented in Intel’s previous generation System on chips (SoC), is simple and robust in terms of implementation. However, the solution is ineffective for some of the next generation Intel SoCs, which have limitations in the number of pins available and the maximum operating frequency of the pins. In this paper, we first dwell into the debug architecture implemented in Columbiaville (CVL), Intel’s…

    The VISA (Visualization of Internal Signal Architecture) based post-silicon debug architecture, implemented in Intel’s previous generation System on chips (SoC), is simple and robust in terms of implementation. However, the solution is ineffective for some of the next generation Intel SoCs, which have limitations in the number of pins available and the maximum operating frequency of the pins. In this paper, we first dwell into the debug architecture implemented in Columbiaville (CVL), Intel’s previous generation Network Interface Controller (NIC) chip, followed by the analysis of its limitations. Further, we discuss the Debug Trace Fabric (DTF) based approach that we have implemented in Connorsville (CNV), Intel’s next generation NIC, and illustrate how it circumvents the aforementioned limitations. We conclude the article with quantitative analysis of the burst window of the DTF solution in order to present a few options of the implementation.

    Other authors
  • A discourse on abusive behaviour in organizations characterized as symbolic violence through the lens of Bourdieu’s theory

    ASCON2021

    The primary purpose of the paper is to approach the theme of abusive behaviour characterizing it as symbolic violence, through the lens of Bourdieu’s theory, which, hitherto, is never attempted.

    Other authors
  • Attacks on Non-Volatile Memories and Hardware Countermeasures

    iSecCon 2021, Europe

    The modern System on Chips (SoC) or Application Specific Integrated Circuits
    (ASICs), require sensitive data such as softstraps, encryption keys and fuses; which
    are stored in Non-Volatile Memories (NVM) because the NVMs are re-configurable
    and can save data even if power is turned off. This intrinsic property of non-volatility
    makes NVM a major target for the attackers. In this paper, we have analyzed
    potential security attacks on the NVMs that are either present in or…

    The modern System on Chips (SoC) or Application Specific Integrated Circuits
    (ASICs), require sensitive data such as softstraps, encryption keys and fuses; which
    are stored in Non-Volatile Memories (NVM) because the NVMs are re-configurable
    and can save data even if power is turned off. This intrinsic property of non-volatility
    makes NVM a major target for the attackers. In this paper, we have analyzed
    potential security attacks on the NVMs that are either present in or accessible via
    Intel ASICs/SoCs. Then we have put forward various hardware counter-measures
    in the chips against those attacks. We have further discussed a modified boot-flow
    and hardware design to prevent attacks on the NVMs by a malicious application
    in the host. We have also portrayed special hardware architecture, in terms of
    incorporating encryption and error detection/correction mechanisms in the interface
    controllers for the NVMs in Intel’s ASICs/SoCs, to secure the NVMs’ contents.
    Finally, we have described Physical Unclonable Functions (PUF), as a more secure
    way of generating secret keys, as opposed to extracting them from the NVMs.

    Other authors
  • Abusive behaviour in organizations – Social Configuration of an Organizational structure, from the realm of Foucault’s theory

    AMSICON2021

    The primary purpose of the paper is to approach the theme of abusive behaviour from the
    realm of Foucault’s theory, which, hitherto, is never attempted.

    Other authors
  • Precision Time Protocol Inspector

    Intel-PSG Technovate 2019

    The tool enables a finer granularity of on-die timestamp accuracy tuning capability

  • Solution-centric Architecture of the PTP features: Asymmetry and Peer delay mechanism, for Intel-PSG 1588-PTP IP solution

    Technovate-2018, Intel-PSG

    This paper explores the solution-centric architectural journey of these two features from IEEE specification to our hardware IP solution, giving an overview of the process.

  • Timing models for PTP in Ethernet networks

    ISPCS 2017 - International IEEE Symposium on Precision Clock Synchronization for Measurement, Control, and Communication

    The article's key objective is to facilitate the pronounced need for timing simulation of the networks at the system level, with Ethernet MAC node timing models and in the process bring out clarity in single lane and multi-lane Ethernet timing models in a unified way across the throughputs from 10Mbps to 100Gbps .

    Other authors
    See publication
  • Hardware Design Considerations for Improving Accuracy in Precision Time Protocol (PTP) Systems

    Technovate 2016, Intel-PSG

    Won the best paper award in the Track 4: Boards and Systems, Applications Design and Architectures, Soft-IP cores, End Markets

    Other authors
    • seng kuan yeow
    • Yu Ying Choo
  • Building a 1588 System Solution - Key learnings

    International IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communications

    The Intel-PSG division focused on FPGAs, has always delivered the hardware Intellectual Property (IP) cores that include both soft cores (RTL code) and hard cores (already routed and supplied with the FPGA), that can integrate well with firmware and application software in a system. The 1588 Precision Timing Protocol (1588-PTP) solution spans both software and hardware and the accuracy reported at a system level has more credibility than the accuracy reported at the hardware level. Hence, the…

    The Intel-PSG division focused on FPGAs, has always delivered the hardware Intellectual Property (IP) cores that include both soft cores (RTL code) and hard cores (already routed and supplied with the FPGA), that can integrate well with firmware and application software in a system. The 1588 Precision Timing Protocol (1588-PTP) solution spans both software and hardware and the accuracy reported at a system level has more credibility than the accuracy reported at the hardware level. Hence, the Intel-PSG has chosen the route of open-source stack available with the Linux and built its 1588 RD (Reference Design) solution comprising its already established 1588 hardware IP. The system solution has achieved an accuracy of around 7ns in an Ordinary Clock system comprising one master clock and one slave clock. This article details the objectives of the 1588 RD solution, the technical process of achieving the objectives and key learnings in the whole exercise. Specifically, the article focuses on the key system level decisions viz., (a) choosing FIFO/DMA/TCAM (b) Timestamping all the packets vs timestamping only the PTP packets. The article further details the software and hardware architecture and their internal design details, the PTP packet flow and the procedure of arriving at the system level accuracy. Key learnings and scope for future work conclude the article.

    Other authors
    • Yu Ying Choo
    • Vince Bridgers
    See publication
  • Building System Solution - A cross functional achievement and key learnings from the past

    Altera Technical Symposium - 2015

    Details the process involved in realizing a networking system fully realized in an FPGA taking a case-study.

  • CE Live! (TM): Carrier-Grade SDN, ALU-No ... More?, Ethernet Speeds, More NFV, and the "CE in the Cloud Age!" - Exclusive Workshop!

    Metanoia, Inc. Google Hangout on Air (A Live Streamed Technical Discussion)

    An analysis of "Carrier-Grade SDN"​ with four engaged international members of the Carrier Ethernet Group. In addition, we look at key issues such as ALU-No ... more (which might be an apt name for the new Alcatel-Lucent-Nokia entity :-)) - and what that means for the industry, the burgeoning NFV market, and the slew of Ethernet speeds (that have been defined and are being defined in the months to come).
    We also explain the unique workshop "CE in the Cloud Age!"​ being organized in…

    An analysis of "Carrier-Grade SDN"​ with four engaged international members of the Carrier Ethernet Group. In addition, we look at key issues such as ALU-No ... more (which might be an apt name for the new Alcatel-Lucent-Nokia entity :-)) - and what that means for the industry, the burgeoning NFV market, and the slew of Ethernet speeds (that have been defined and are being defined in the months to come).
    We also explain the unique workshop "CE in the Cloud Age!"​ being organized in conjunction with Lightreading's Big Telecom Event (BTE), and what people will learn at this exclusive workshop (we limit attendance to under 100). Plus ... we give away up to 5 FREE passes to the workshop AND to BTE to the best participants in this Hangout.

    This is an opportunity for networking practitioners to come up to speed on the latest packet networking technologies (as reflected in the Carrier Ethernet Group) without the B.S. :-), and learn about industry best-practices that we believe will enable them to be better practitioners and technical experts!

    Other authors
    See publication
  • A Unified Synchronization Solution for Ethernet

    Ethernet Technology Summit

    Explores 1588 PTP as unified synchronization protocol overcoming the roadblocks from the Syntonization perspective.

    See publication
  • CE Live! ™: Network Performance, Lifecycle Service Orchestration, Viva Net Neutrality (?) , Service Chaining, & Exploding Mobile Video!

    Metanoia, Inc. Google Hangout on Air (A Live Streamed Technical Discussion)

    An analysis of key issues in the Carrier Ethernet Group the week ending March 1st, 2015. What the FCC's big decision supporting Title II means for broadband, what's up with Lifecycle Service Orchestration (LSO) and the completeness of the Type 2 EPL (Ethernet Private Line) spec. How to service chain VNF's for NFV, and the explosion of mobile video are some of the issues we cover here.

    This is an opportunity for networking practitioners to come up to speed on the latest packet networking…

    An analysis of key issues in the Carrier Ethernet Group the week ending March 1st, 2015. What the FCC's big decision supporting Title II means for broadband, what's up with Lifecycle Service Orchestration (LSO) and the completeness of the Type 2 EPL (Ethernet Private Line) spec. How to service chain VNF's for NFV, and the explosion of mobile video are some of the issues we cover here.

    This is an opportunity for networking practitioners to come up to speed on the latest packet networking technologies (as reflected in the Carrier Ethernet Group) without the B.S. :-), and learn about industry best-practices that we believe will enable them to be better practitioners and technical experts!

    Other authors
    See publication
  • 1588 Systems Deployment with Altera's 1588 HW IP

    Altera Penang Embedded Symposium

    Systems Development using Altera's 1588 HW IP with best-in-class Accuracy

  • The practical SV/OVM verification methodology for an in-house IP in Vitesse

    Mentor Graphics User Conference :: U2U, 2012

    To bring out the practical facets of verification using SV/OVM methodology

    Other authors
    See publication
  • Human Resource Planning – THEN and NOW

    Prabandhan: Indian Journal of Management

    Human Resource Planning – THEN and NOW, Sept 2012, Prabandhan: Indian Journal of Management, pp 27-31.

    See publication

Patents

  • Method for generating IEEE 1588 TX timestamps in an Ethernet channel subject to data valid and unknown latency components that can be used for 1-step or 2-step PTP messages

    Issued US 11349587

    Timestamping in Server, Data Center and Network Platforms

    Other inventors
  • One-step time stamping of synchronization packages for networked devices

    Issued US 10931391

    Consists of two sections focusing on timestamping of the networked devices, when the interfacing device such as MACSec with 1588 block is (a)open to the design team with all the internal design details known unambiguously (b)closed to the design team, as a black box.

  • Driver for Network Timing Systems

    Issued US 10394734

    Firmware Driver implementation for effective timing closure in timing systems.

    See patent
  • Multi-Tier Time-Synchronization Architecture

    Issued US 10374734

    A scalable, reusable, modular architecture for time-synchronization in computer networks

    See patent
  • Techniques For Determining Timestamp Inaccuracies In A Transceiver

    Filed US IPG-AB8340-US

    An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a…

    An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.

  • High Performance Computing (HPC) Server Chassis/Rack Dynamically Adaptable To Different Applications Running On A DC/Cloud

    Filed 202341061837

    High Performance Computing (HPC)
    Server Chassis/Rack Dynamically Adaptable To Different Applications
    Running On A DC/Cloud

    Other inventors
  • Hardware Logic Implementation of High-Throughput Configurable-CRC Computation Using Data Folding Technique

    Filed AE6062

    Hardware Logic Implementation of High-Throughput Configurable-CRC Computation Using Data Folding Technique :: 256Gbps to 2Tpbs line-rate demonstrated.

    Other inventors

Honors & Awards

  • 2016 Patent Campaign Winner

    Intel-PSG (Formerly Altera)

    4 disclosures filed and 2 chosen for filing

  • 2015 Patent Campaign Winner

    Intel-PSG (formerly Altera)

    5 disclosures filed, 2 chosen for filing

  • 2015 Altera Engineering Excellence Award

    Altera

    Realization of a reference design involving the complete system solution

Recommendations received

View Chandra Sekhar’s full profile

  • See who you know in common
  • Get introduced
  • Contact Chandra Sekhar directly
Join to view full profile

Other similar profiles

Explore collaborative articles

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

Explore More

Others named Chandra Sekhar Mallela in India

Add new skills with these courses