Bharadwaj Amrutur

An adaptive digital baseband receiver is described in which operating parameters of the receiver, such as bit-widths and operating frequencies, are determined that achieve a target bit-error-ratio (BER) as a function of received signal-to-noise ratio (SNR) and interference levels in a wireless channel and enable the receiver to consume a minimum amount of power. Over consumption of power may be avoided due to a functional relationship between optimal resolution and input signal conditions. In… Show more

An adaptive digital baseband receiver is described in which operating parameters of the receiver, such as bit-widths and operating frequencies, are determined that achieve a target bit-error-ratio (BER) as a function of received signal-to-noise ratio (SNR) and interference levels in a wireless channel and enable the receiver to consume a minimum amount of power. Over consumption of power may be avoided due to a functional relationship between optimal resolution and input signal conditions. In exemplary embodiments, the adaptive digital receiver is provided that adjusts bit-widths and operating frequency at power efficient levels while meeting a target BER. Simulations can be used to determine a relation between bit-width, operating frequency, and input signal conditions, for example. Show less

Embodiments of the disclosure relate to a low drop diode equivalent circuit. Piezoelectric device based vibration energy harvesting requires a rectifier for conversion of input ac to usable dc form. Power loss due to diode drop in rectifier is a significant fraction of the already low levels of harvested power. The low-drop-diode equivalent can replace the rectifier diodes and minimise power loss. The diode equivalent mimics a diode using linear region operated MOSFET. The diode equivalent is… Show more

Embodiments of the disclosure relate to a low drop diode equivalent circuit. Piezoelectric device based vibration energy harvesting requires a rectifier for conversion of input ac to usable dc form. Power loss due to diode drop in rectifier is a significant fraction of the already low levels of harvested power. The low-drop-diode equivalent can replace the rectifier diodes and minimise power loss. The diode equivalent mimics a diode using linear region operated MOSFET. The diode equivalent is powered directly from input signal and requires no additional power supply for its control. Power used by the control circuit is kept at a value which gives an overall output power improvement. The diode equivalent replaces the four diodes in a full wave bridge rectifier, which is the basic full-wave rectifier and is a part of the more advanced rectifiers like switch-only and bias-flip rectifiers. Show less

Les modes et formes de réalisation de l'invention concernent un système et un procédé visant à optimiser la consommation d'énergie dans un convertisseur analogique-numérique (CAN). Le système forme un convertisseur à approximations successives (SAR-CAN) de 8 bits comportant un tampon d'entrée et de référence. La résolution du CAN peut être réglée de 8 à 1 bit linéairement, sur la base de la condition de gamme dynamique. Une commutation de convertisseur numérique-analogique (CNA) économe en… Show more

Les modes et formes de réalisation de l'invention concernent un système et un procédé visant à optimiser la consommation d'énergie dans un convertisseur analogique-numérique (CAN). Le système forme un convertisseur à approximations successives (SAR-CAN) de 8 bits comportant un tampon d'entrée et de référence. La résolution du CAN peut être réglée de 8 à 1 bit linéairement, sur la base de la condition de gamme dynamique. Une commutation de convertisseur numérique-analogique (CNA) économe en énergie permet d'atténuer la décharge du CAN, et permet une consommation d'énergie moindre par rapport aux procédés classiques. L'utilisation d'un échantillonnage d'entrée ping-pong dans le CAN permet de réduire la condition de bande passante du tampon d'entrée et la vitesse d'horloge selon un facteur de deux. Le procédé de conversion est activé uniquement par l'intermédiaire de la logique intégrée de rejet de bruit de fond, pour assurer que le bruit n'est pas traité. Ce procédé de conversion permet de réduire à la fois la consommation d'énergie et le débit de sortie. Show less

Design of a disposable screen printed electrode (SPE) for sensing percentage glycated hemoglobin using electrochemistry is disclosed. SPE has four electrodes, one working electrode for the detection of glycated hemoglobin, one working electrode for the detection of hemoglobin and the other two electrodes are counter and reference electrodes that are common for both detection schemes. It also has a cellulose acetate membrane with lysis agents and surfactant embedded in it. Lysis agents lyse… Show more

Design of a disposable screen printed electrode (SPE) for sensing percentage glycated hemoglobin using electrochemistry is disclosed. SPE has four electrodes, one working electrode for the detection of glycated hemoglobin, one working electrode for the detection of hemoglobin and the other two electrodes are counter and reference electrodes that are common for both detection schemes. It also has a cellulose acetate membrane with lysis agents and surfactant embedded in it. Lysis agents lyse erythrocytes and release hemoglobin. Surfactants modify hemoglobin structure and enhance the rate the electron transfer and thereby the output signal during the electrochemical analysis. The SPE is low cost and user friendly. The only input from the user is a drop of blood. Show less

Des modes de réalisation de l'invention portent sur un procédé et un système de test intégré de signaux analogiques avec supplément de superficie minimal, pour mesurer des tensions sur puce d'une manière entièrement numérique. Le procédé est bien adapté à une architecture distribuée, dans laquelle le routage de signaux analogiques sur de longs chemins est réduit au minimum. Une horloge est routée en série vers les têtes d'échantillonnage (SpM) placées au niveau des nœuds de tensions de test… Show more

Des modes de réalisation de l'invention portent sur un procédé et un système de test intégré de signaux analogiques avec supplément de superficie minimal, pour mesurer des tensions sur puce d'une manière entièrement numérique. Le procédé est bien adapté à une architecture distribuée, dans laquelle le routage de signaux analogiques sur de longs chemins est réduit au minimum. Une horloge est routée en série vers les têtes d'échantillonnage (SpM) placées au niveau des nœuds de tensions de test analogiques. Cette tête d'échantillonnage, présente au niveau de chaque nœud de test, qui est constituée d'une paire de cellules à retard et d'une paire de bascules, convertit localement la tension de test en un défaut d'alignement entre deux signaux sous-échantillonnés, donnant ainsi naissance à autant de paires de signaux sous-échantillonnés que le nombre de nœuds. Pour mesurer une certaine tension analogique, la paire de signaux sous-échantillonnés correspondante est appliquée à une unité de mesure de retard (DMU) pour mesurer le défaut d'alignement entre les signaux de cette paire. Show less

A technique for a delay measurement system to measure the skews in a clock distribution network is presented. It uses the principle of sub-sampling to measure and amplify small clock skews and determine an estimate of clock skew by further manipulation if these sampled measurements. The technique can be applied to measure clock skew on a computer chip, between bit-line of a communication bus, or between elements connected by an electronic or optical interconnect.

Embodiments of the disclosure relate to an all-digital technique for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A sub-sampling technique based delay measurement unit capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The delay generation system periodically measures and corrects the error and maintains it at the minimum… Show more

Embodiments of the disclosure relate to an all-digital technique for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A sub-sampling technique based delay measurement unit capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. A significant improvement in accuracy is obtained for a commercial programmable delay generator chip. The time-precision trade-off feature of the delay measurement unit is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter. Show less

A porous membrane for lysis of a cell population enriched from a biological sample, and isolation of cellular components is provided. The porous membrane contains embedded lysing agents to perform lysing. The biological sample is brought into contact with the membrane. Lysis occurs through the action of the embedded lysing agents on the biological sample. The pores of the porous membrane are designed to have dimensions to allow only a desired type of cellular component(s) resulting from lysis… Show more

A porous membrane for lysis of a cell population enriched from a biological sample, and isolation of cellular components is provided. The porous membrane contains embedded lysing agents to perform lysing. The biological sample is brought into contact with the membrane. Lysis occurs through the action of the embedded lysing agents on the biological sample. The pores of the porous membrane are designed to have dimensions to allow only a desired type of cellular component(s) resulting from lysis to pass through the membrane, thereby achieving isolation of the desired cellular component(s). The action of lysing agents is combined with the filtration properties of porous membranes resulting in an easy-to-use and cost-effective technique. Show less

A system and method to measure a delay of an individual logic gate in an unmodified form on a chip using a digitally reconfigurable ring oscillator (RO) that is on the chip is provided. A system of linear equations is established for different configuration settings of the ring oscillator and solved to determine a delay of an individual gate.

A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires… Show more

A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires carry sensing and actuation signals between the column of sensing electrodes and a processing chip. The signals may be amplified by CMOS sensing chips between the source and destination of the signals. In this way, signals may be received from and sent to a dense matrix of sensing electrodes spanning a large geographic area with little or no degradation. Show less

System and methods for reducing third harmonic distortion produced by nonlinear amplifiers are disclosed. A system may include an amplifier circuit with an amplifier transistor such that the amplifier is capable of exhibiting an amplifier output signal containing third harmonic distortion. Further, a system may include a nonlinear feedback circuit with a first feedback transistor operating in Triode mode that produces a feedback electronic signal containing a feedback third harmonic component… Show more

System and methods for reducing third harmonic distortion produced by nonlinear amplifiers are disclosed. A system may include an amplifier circuit with an amplifier transistor such that the amplifier is capable of exhibiting an amplifier output signal containing third harmonic distortion. Further, a system may include a nonlinear feedback circuit with a first feedback transistor operating in Triode mode that produces a feedback electronic signal containing a feedback third harmonic component. In addition, the nonlinear feedback circuit may be configured to the amplifier circuit in negative feedback such that the feedback third harmonic component of the feedback electronic signal reduces the third harmonic distortion of the amplifier output signal. A system may also provide an output signal that has less third harmonic distortion than the amplifier output signal. Show less

An example method for optimizing power consumption of digital circuits using dynamic voltage and threshold scaling (DVTS) is provided. A propagation delay of a signal through a portion of the circuit is determined and if the propagation delay does not meet a specified delay requirement, then a supply voltage and/or threshold voltage of the circuit is adjusted. Subsequently, a power consumption level of the circuit is determined and compared to previous power consumption levels. The supply… Show more

An example method for optimizing power consumption of digital circuits using dynamic voltage and threshold scaling (DVTS) is provided. A propagation delay of a signal through a portion of the circuit is determined and if the propagation delay does not meet a specified delay requirement, then a supply voltage and/or threshold voltage of the circuit is adjusted. Subsequently, a power consumption level of the circuit is determined and compared to previous power consumption levels. The supply and/or threshold voltage of the circuit can be readjusted to enable the circuit to meet specified power consumption requirements and the specified delay requirement, for example. Show less

A low noise amplifier (LNA) system with controllable linearity and noise figure versus power consumption is provided. The system comprises two control inputs for tuning. One input controls an effective transistor width, and the other input controls bias current. Changes to the effective transistor width alter a gain that is applied to a signal, and changes to the bias current alter a power consumption of the system. For more stringent signal specifications, an impedance matched inductive… Show more

A low noise amplifier (LNA) system with controllable linearity and noise figure versus power consumption is provided. The system comprises two control inputs for tuning. One input controls an effective transistor width, and the other input controls bias current. Changes to the effective transistor width alter a gain that is applied to a signal, and changes to the bias current alter a power consumption of the system. For more stringent signal specifications, an impedance matched inductive degeneration variation of the LNA is provided. Show less

Blocks of input data are received. The input data comprises packets of information words. The packets are preceded and followed by control words. A master transition is appended to the beginning of each block to form a respective frame for transmission. The master transition has a sense that depends on whether the block contains any control words. Additionally, for each block that contains one or more control words, a TYPE word indicating a structural property of the block is generated, the… Show more

Blocks of input data are received. The input data comprises packets of information words. The packets are preceded and followed by control words. A master transition is appended to the beginning of each block to form a respective frame for transmission. The master transition has a sense that depends on whether the block contains any control words. Additionally, for each block that contains one or more control words, a TYPE word indicating a structural property of the block is generated, the block is condensed to accommodate the TYPE word, and the TYPE word is inserted into the block. The coding method provides a very low overhead (3.125%) when implemented as a 64b/66b code. Show less

The frame of data that is decoded is one of a set of frames that represent a packet of information words, and that additionally represent coded control words preceding and following the packet. The frames each include a master transition and a payload field. The payload field either is composed exclusively of ones of the information words, or includes a TYPE word that defines the structure of the payload field. The master transition is in a first state when the payload field is composed… Show more

The frame of data that is decoded is one of a set of frames that represent a packet of information words, and that additionally represent coded control words preceding and following the packet. The frames each include a master transition and a payload field. The payload field either is composed exclusively of ones of the information words, or includes a TYPE word that defines the structure of the payload field. The master transition is in a first state when the payload field is composed exclusively of ones of the information words, and is otherwise in a second state. In the method, a determination is made of whether the master transition is in the first state. When the master transition is in the first state, the payload field is adopted as a block of received data. When the master transition is not in the first state, the TYPE word is extracted from the payload field, the payload field is expanded in response to the TYPE word, and the payload field, after expansion, is adopted as a block of received data. Show less

The passive measurement platform may be incorporated into a network router or used in conjunction with a network router. The passive measurement platform receives an OSI data packet, extracts the OSI Layer 3 from the OSI data packet, extracts headers from the OSI Layer 3, generates a unique packet label corresponding to the headers, generates a timestamp, and creates a data packet that includes the headers, packet label, and timestamp. The timestamp is GPS-based to minimize problems associated… Show more

The passive measurement platform may be incorporated into a network router or used in conjunction with a network router. The passive measurement platform receives an OSI data packet, extracts the OSI Layer 3 from the OSI data packet, extracts headers from the OSI Layer 3, generates a unique packet label corresponding to the headers, generates a timestamp, and creates a data packet that includes the headers, packet label, and timestamp. The timestamp is GPS-based to minimize problems associated with frequency drift and counter overflow. Both the push and pull models of data retrieval are used to conserve network bandwidth. Show less

The network monitoring system (100, 200, 300) comprises a network router (102, 202, 302) with built-in monitoring data gathering. The network router includes channels (e.g., CH1) through which data pass in packets. Each of the packets includes a packet header. The network router additionally includes a header copier (150, 262) and a packet generator (164, 264). The header copier generates a header copy from the packet header of at least some of the packets. The packet generator receives the… Show more

The network monitoring system (100, 200, 300) comprises a network router (102, 202, 302) with built-in monitoring data gathering. The network router includes channels (e.g., CH1) through which data pass in packets. Each of the packets includes a packet header. The network router additionally includes a header copier (150, 262) and a packet generator (164, 264). The header copier generates a header copy from the packet header of at least some of the packets. The packet generator receives the header copies and forms monitoring data packets from them. Each monitoring data packet additionally represents temporal data relating to the header copies included in it. A method of obtaining performance data relating to a data transmission network (e.g., 220) that includes a node (e.g., 202) passes (402) data through the node in packets. Each of the packets includes a packet header. At least some of the packet headers are copied (404) to obtain respective header copies as monitoring data from which monitoring data packets are formed (406). The monitoring data packets additionally represent temporal data relating to the header copies included in them. The monitoring data packets are transmitted (408) and the performance data are generated (410) from the monitoring data contained in the monitoring data packets. Show less

A communications system and method are disclosed. A transmitter (2) includes a scrambler (5) for scrambling original data, an ECC encoder (6) for converting scrambled data into ECC data, and a serializer for converting the ECC data into a serial stream. A receiver (3) includes a frame recoverer (9) for converting the serial data into frame data, an ECC decoder (10) from converting the frame data into ECC data and error indications, and a descrambler (14) for restoring the original data. By… Show more

A communications system and method are disclosed. A transmitter (2) includes a scrambler (5) for scrambling original data, an ECC encoder (6) for converting scrambled data into ECC data, and a serializer for converting the ECC data into a serial stream. A receiver (3) includes a frame recoverer (9) for converting the serial data into frame data, an ECC decoder (10) from converting the frame data into ECC data and error indications, and a descrambler (14) for restoring the original data. By using the results of the ECC decoding to convert the serial data into frame data, line decoding is unnecessary, thereby reducing channel usage. Show less