DPIIND

What a wonderful time we had this #Deepawali! Our Bangalore #DPIIND team came together to celebrate the joy of Diwali.  The team created a beautiful Rangoli, filling our space with vibrant colors and excitement. it was a wonderful time to come together, share sweets & Gifts. Diwali celebrations are always full of joy, and the excitement truly begins with the preparations!  Here are some glimpses of how we embraced this beautiful time and made it unforgettable! 

Hi Everyone, We are hiring #PhysicalDesignEngineer #DPIIND is expanding the team! we are looking for Physical Design Engineer to join us. //Email your resumes to [email protected] and pls mention Position/location in subject.// Please find the JD Below: Position: Physical Design Engineer Experience : #2 Years Location: #Bangalore Skill: #PhysicalDesign & #STA We are looking for 2 years PD, STA Experienced Engineers. Looking for a people who can join immediate to 30 day’s notice period. Interested people pls email your updated resume to [email protected] Tools: #ICC or #Innovus for PnR, Encounter for #FloorPlan #PD #Hiring #STA

Hello All,   We are thrilled to announce the grand opening of our new office..! This Milestone marks a significant step in our journey. A big thank you to our dedicated team and parents who have made this possible. Here’s to new beginnings and continued success. Our new space represents more than just a physical location; it signifies our growth, our commitment to innovation, and our dedication to providing a better work environment for our team.   Stay tuned for more updates and exciting news from our team!

Hello All, We are looking for HR Recruiter/ #TalentAcquisition to work on our Internal requirements (VLSI Industry). Person should be good at working on #VLSIrequirement and must be experienced in the same stream only. Interested candidates may share their updated resume to [email protected] Experience: 2 Yrs Location: Bangalore – Marathahalli NP: Immediate #Recruitment #HR #VLSI #PD

Dear Connections, We are looking for DFT Engineers, Exp : 3 yrs Location: Bangalore Notice: IMM to 30 days Experience in DFT Scan Insertion, ATPG at IP and Soc level Hands on Experience in ATPG Timing and No-Timing Simulations Knowledge on Simulations, Scan/ATPG patterns, debug, test and characterization. Interested Engineers can share resumes to [email protected] Suvarna Latha ChandraSekharaReddy Tumma hima bindu Venkata Naveen Lakshmikanth Ganji SRUJANA TUMU #dft #vlsi #semiconductor #immediatehiring #bangalorejobs #careergrowth

Hi Everyone, We do have immediate hiring for the below requirement for project. Please find the JD Below: Physical Design Engineer/Sr. PD Engineer/Lead Experience : 2 Years Location: Bangalore Skill: Physical Design & STA We are looking for 2 years PD, STA Experienced Engineers. Looking for a people who can join immediate to 30 day’s notice period. Interested people pls email your updated resume to [email protected] #pd #sta #hiring #vlsi

Hello Jobseekers, Greetings from DPIIND…! DPIIND Services Private Limited #MegaWeekendDrive for #PhysicalDesign/ #STA TRAINED FRESHERS on 27 July 2024 – Saturday. Details are below.. Please join us fantastic technical team to full fill your dreams. Welcoming you to be part of our family. 

Hello Jobseekers, Greetings from DPIIND…! DPIIND Services Private Limited #MegaWeekendDrive for #PhysicalDesign/ #STA TRAINED FRESHERS on 27 July 2024 – Saturday. Details are below.. Please join us fantastic technical team to full fill your dreams. Welcoming you to be part of our family. 

Hello All, We are looking for 3 years PD, STA Experienced Engineers. Looking for a people who can join immediate to 30 day’s notice period. Senior Physical Design Engineer & Lead Experience : 3 Years Location: Bangalore Skill: Physical Design & STA Interested people may email your resume to [email protected] #PD #STA #PhysicalDesign #Floorplan #PNR

Hello Everyone, Here is an excellent opportunity with #DPIIND for the Freshers of BE/B. Tech (ECE/CS/EEE)/ME/M. Tech - 2024/2023 pass out students for #Bangalore location. Below is the #MandatorySkillSet and #ReferenceTextBooks details to prepare accordingly and get selected to join with DPIIND Family for a good foundation training and career growth with our Immediate recruitment. #ReferenceTextBooks: Digital Design by Morris Mano Verilog HDL by Samir Palnitkar Fundamentals of CMOS VLSI - A Conceptual Approach  V. S. Bagad #DigitalElectronics: · Universal gates · Construction of all 2-input gates using 2X1 MUX · Differences b/w combinational & sequential circuits · Differences b/w latch & flipflop · Different types of flip flops · Gate-level circuit diagrams of D-Latches, D-Flipflops · Master Slave D-Flipflop & Edge triggered D-Flipflop gate level circuit diagrams · Able to draw the circuit diagrams based on Boolean equations. · Need to learn the construction of Boolean equations based on functionalities. · Differences b/w synchronous & asynchronous circuits · State machines fundamentals & their applications · Differences b/w Melay & Moore State machines · Meta-stability concepts · Race-around condition · Clock period calculations of a sequential circuit. · Setup & hold times. How to fix these violations in the designs? #VerilogHDL/VHDL: · Need of HDLs over Software languages · Verilog programing fundamentals · For the given code, need to write the circuit diagrams · System tasks · Simulation Dump commands · Need to write the proper Test Benches (TBs) for given design PHYTON / PERL / TCL: (Anyone scripting language) · Syntax of PHYTON programs · Able to write the small programs using the scripting languages #CMOSFundamentals: · Advantages of CMOS over NMOS/PMOS alone circuits · Able to implement the basic gates using CMOS circuits · Need to understand the optimization concepts while implementing the CMOS circuits Interested one's please share your updated resume to [email protected] / [email protected] #jobs #hiring #DFT #Verilog #DigitalElectronics #CMOS