CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

• Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.

• Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

• Higher-order functions, with type inference, result in designs that are fully parametric by default.

• Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

• Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

• Prelude library containing datatypes and functions for circuit design

To use the library:

• Import Clash.Prelude

• Alternatively, if you want to explicitly route clock and reset ports, for more straightforward multi-clock designs, you can import the Clash.Explicit.Prelude module. Note that you should not import Clash.Prelude and Clash.Explicit.Prelude at the same time as they have overlapping definitions.

A preliminary version of a tutorial can be found in Clash.Tutorial, for a general overview of the library you should however check out Clash.Prelude. Some circuit examples can be found in Clash.Examples.

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Manual Flags

Name	Description	Default
doctests	You can disable testing with doctests using `-f-doctests`.	Enabled
benchmarks	You can disable testing with benchmarks using `-f-benchmarks`.	Enabled

Use -f <flag> to enable a flag, or -f -<flag> to disable that flag. More info

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• clash-prelude-0.99.3.tar.gz [browse] (Cabal source package)
• Package description (as included in the package)

Maintainer's Corner

Package maintainers

• ChristiaanBaaij, QBayLogic

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Candidates

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