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Communication framework for RTL simulation and emulation.
Python 260 20
A configurable RTL to bitstream FPGA toolchain
Python 255 7
Universal Memory Interface (UMI)
Verilog 138 9
Demo: how to create a custom EBRICK
SystemVerilog 15
Generate a website from markdown with a minimum of fuss.
Svelte 9
Docker image with RTL simulation tools preinstalled
Dockerfile
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