A Software Defined Radio development board.
Initial project codename Icyradio originated from the device family name of the FPGA used in the first version (ICE40). Coincidently, the device family name of the FPGA used in this version (Artix) also resembles a very cold region, the Arctic, hence, the project codename still holds some of its sense 😊.
- XC7A100T-2FGG484 - FPGA
- Raspberry Pi CM4 - Raspberry Pi Compute Module 4
- MT41K256M16TW-125 - DDR3 RAM
- AD9361 - Agile RF Transceiver
- SI5351C - System clock synthesizer
- 8V97003 - Frequency Synthesizer for external mixer support
- ADAU1372 - Audio CODEC
- UPD301C - USB Power Delivery controller
- LT7182S - Main Buck regulator
Note: From v2 onwards, the only components in this repository are hardware related, no specific application software, like in v1 branches. Applications that use this hardware are kept in a separate repository The goal of this project is to develop a flexible and feature rich SDR platform for tinkering. It will include, among other features, a mmWave synthesizer controlled by software to allow external mixers to be attached to the SDR and extend its frequency range (i.e. for 5G applications), and also allow interfacing to a Raspberry Pi Compute Module 4 for standalone operation.
- vivado - FPGA toolchain
- arm-none-eabi-gcc - PD Controller MCU toolchain
- Device CMSIS - CMSIS headers defining the MCU memories, peripherals, etc...
- Core CMSIS - CMSIS headers defining the ARM Cores
- armmem - ELF file analyzer (required for the MCU Makefiles to work)
- SoapySDR - Vendor and platform neutral SDR support library
TODO (In the meantime, check the github workflows)
TODO
TODO
- The WP pin of the LT7182S regulator was left floating, with a placeholder resistor for pulling it up later, assuming it had an internal pulldown. Turns out it is floating, and thus it can be sampled internally as 1, write-protecting the device and forbidding configuration commands. A quick fix is to scrape a tiny bit of the ground plane near the WP resistor (R1120) pad, and shunting it to GND there with a blob of solder. The figure below exemplifies the process. The solder blob is marked in blue.
- The FPGA INIT and DONE LED markings on the PCB are swapped (oops). In the picture below, it can be seen that D202 connects to the FPGA_DONE signal, yet it's labelled INIT. The FPGA_INIT signal connects to D201, and is labelled as DONE. It is merely an aesthetic problem, and does not affect functionality at all!
- João Silva - vankxr
The content of this repository is licensed under the GNU General Public License v3.0.