A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
embedded
fpga
hls
xilinx
vivado
xilinx-fpga
basys3
xilinx-vivado
microblaze
axi
artix
axi-stream
vivado-ip-integrator
artix-7
xilinx-hls
vitis
axi-lite
xilinx-vitis
vivado-vitis
vitis-hls
-
Updated
Dec 3, 2023 - C