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33 public repositories
matching this topic...
A FPGA friendly 32 bit RISC-V CPU implementation
Updated
Sep 23, 2024
Assembly
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Updated
Sep 15, 2024
Verilog
80186 compatible SystemVerilog CPU core and FPGA reference design
An FPGA-based RISC-V CPU SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU SoC,包含一个简单且可扩展的外设总线。
Updated
Sep 14, 2023
SystemVerilog
A Forth CPU and System on a Chip, based on the J1, written in VHDL
Updated
Mar 19, 2024
VHDL
🌳 A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Updated
Nov 8, 2023
Scala
Mostly AVR compatible FPGA soft-core
Updated
Sep 30, 2021
Verilog
u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
Updated
Jul 25, 2023
Verilog
Soft-core uController POC using the risc16f84 pic clone and sdcc c-compiler
Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware
Updated
Aug 24, 2020
Verilog
A 16 bit softcore processor implemented in VHDL
Updated
Nov 12, 2020
VHDL
Trabalho de conclusão de curso de título Integração de ramais analógicos com FPGA utilizando processador softcore
Trying to implement a soft core SoC
Updated
Apr 6, 2019
Verilog
A cycle-accurate VHDL model for MCS-48 and UPI devices
Updated
Jan 23, 2023
VHDL
Set of basic image processing systems implemented for learning purposes.
Updated
Sep 13, 2021
VHDL
Implementation of a soft-core CPU and an assembler
Updated
Jan 19, 2021
VHDL
A RISC/CISC 32 bit softcore processor in VHDL
Updated
Jul 23, 2022
VHDL
EC16-CPU running ECMON @ 20MHz on an ICE40UP5K-SG48 (ICY40-Board)
Updated
Jun 17, 2024
VHDL
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