rocket-chip
Here are 21 public repositories matching this topic...
SonicBOOM: The Berkeley Out-of-Order Machine
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Aug 14, 2024 - Scala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Aug 16, 2024 - Scala
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
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Aug 16, 2024 - Scala
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
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Jan 23, 2020 - Scala
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
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Nov 14, 2018 - SystemVerilog
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
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Nov 24, 2019 - C
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale board (ZCU102)
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Mar 21, 2023 - Tcl
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
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Jul 14, 2020 - C
A fault-injection framework using Chisel and FIRRTL
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Feb 1, 2023 - Scala
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.
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Jan 23, 2024 - Scala
Network components (NIC, Switch) for FireBox
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Jun 25, 2024 - Scala
BOOM's Simulation Accelerator.
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Dec 16, 2021 - Scala
A simple baremetal program template for RISC-V inspired from riscv benchmark tests
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Apr 17, 2018 - C
Parallella RISC-V Prebuilt Images
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Aug 18, 2016
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Jan 9, 2021 - Scala
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