XLS: Accelerated HW Synthesis

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Intermediate Language (IL) for Hardware Accelerator Generators

DaCe - Data Centric Parallel Programming

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

FPGA Accelerator for CNN using Vivado HLS

PandA-bambu public repository

A Compiler for the Popr Language

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

Allo: A Programming Model for Composable Accelerator Design

Time-sensitive affine types for predictable hardware generation

CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture

Polyphony is Python based High-Level Synthesis compiler.

A formally verified high-level synthesis tool based on CompCert and written in Coq.

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

Tutorials on HLS Design