ucb-bar / chipyard Star 1.6k Code Issues Pull requests Discussions An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha Updated Oct 21, 2024 Scala
firesim / firesim Star 875 Code Issues Pull requests Discussions FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility cloud fpga hardware simulation boom rocket-chip risc-v datacenter on-prem firesim Updated Oct 20, 2024 Scala
firesim / FireMarshal Star 76 Code Issues Pull requests Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim. linux fedora spike distro qemu buildroot workload firesim chipyard Updated Oct 19, 2024 Python
CSL-KU / bru-firesim Star 3 Code Issues Pull requests BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors firesim bru bandwidth-regulation-unit Updated Mar 29, 2021 Python