mihir8181 / VLSI-Design-Digital-System Star 13 Code Issues Pull requests This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details digital simulation logic-gates alu vlsi multiplexer cadence-virtuoso andgate orgate 1bitfulladder logicgates vlsi-circuits vlsi-design vlsi-designing vlsi-project 4bitadder 8isto1mux 4bitdivider 4bitmultiplier dflipflop Updated Mar 22, 2019
Nikronic / Microelectronic-Circuits Star 4 Code Issues Pull requests Assignment of Microelectronic Circuits using HSPICE to simulate some of CMOS gates logics. or cmos nor inverter hspice dflipflop holdtime setuptime Updated Jun 8, 2019 SourcePawn
Mhd-Shah / Verification-of-D--flipflop-using-UVM Star 2 Code Issues Pull requests Verification of D-FF using UVM on EDA playground verilog systemverilog verilog-hdl dflipflop rtl-design uvm-verification Updated Nov 19, 2023 SystemVerilog
nikhilranjan54 / assignment-internship Star 0 Code Issues Pull requests assignments on flipflop dflipflop jkflipflop Updated May 16, 2019 C
ChristyRachel / VHDL-Programming Star 0 Code Issues Pull requests dflipflop Updated Jul 23, 2020 VHDL
CodiieSB / VHDL-DFlipFlop Star 0 Code Issues Pull requests The VHDL code describes a D flip-flop with synchronous reset functionality. vhdl xilinx-vivado vhdl-code dflipflop Updated Feb 28, 2024 VHDL
akorkos / digital-electronic-systems Star 0 Code Issues Pull requests Digital Circuits made with VHDL ram encoder mux comparator multiplier full-adder dflipflop jkflipflop led-counter Updated Jul 8, 2024 VHDL