Opensource DDR3 Controller
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Updated
Aug 16, 2024 - Verilog
Opensource DDR3 Controller
SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
mirror of https://git.elphel.com/Elphel/eddr3
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
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