GitHub - syedarafia13/RISCV-CORE-FPGA: This repository contains RISCV (RV32I) Single Cycle Processor RTL design in SystemVerilog and Testbench in C for fpga.

syedarafia13 / RISCV-CORE-FPGA Public

This repository contains RISCV (RV32I) Single Cycle Processor RTL design in SystemVerilog and Testbench in C for fpga.

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
rafia_fpga_core.cache		rafia_fpga_core.cache
rafia_fpga_core.hw		rafia_fpga_core.hw
rafia_fpga_core.ip_user_files		rafia_fpga_core.ip_user_files
rafia_fpga_core.runs		rafia_fpga_core.runs
rafia_fpga_core.srcs		rafia_fpga_core.srcs
rafia_fpga_core.xpr		rafia_fpga_core.xpr

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