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💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

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RISCV-Simulator

Warning: This branch is for online judge only. For details and documentation, refer to seq or pipeline branch.

Branch Build Status Note
seq Build Status A sequential implementation. First edition. No feed forward.
feedforward Build Status Second edition. Based on seq. Feeding forward runs faster. (Though I don't like it.)
pipeline Build Status Pipelined version. Based on seq. Handle hazard by forwarding. Two-level adaptive predictor.
master Build Status For online judge

RISCV-Simulator implemented in C . Support RV32I ISA.

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💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

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