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Add bare metal riscv32 target. #122696

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Mar 21, 2024
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Add bare metal riscv32 target. #122696

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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1621,6 1621,7 @@ supported_targets! {
("riscv32i-unknown-none-elf", riscv32i_unknown_none_elf),
("riscv32im-risc0-zkvm-elf", riscv32im_risc0_zkvm_elf),
("riscv32im-unknown-none-elf", riscv32im_unknown_none_elf),
("riscv32ima-unknown-none-elf", riscv32ima_unknown_none_elf),
("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf),
("riscv32imc-esp-espidf", riscv32imc_esp_espidf),
("riscv32imac-esp-espidf", riscv32imac_esp_espidf),
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29 changes: 29 additions & 0 deletions compiler/rustc_target/src/spec/targets/riscv32ima_unknown_none_elf.rs
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@@ -0,0 1,29 @@
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};

pub fn target() -> Target {
Target {
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
llvm_target: "riscv32".into(),
metadata: crate::spec::TargetMetadata {
description: None,
tier: None,
host_tools: None,
std: None,
},
pointer_width: 32,
arch: "riscv32".into(),

options: TargetOptions {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(),
max_atomic_width: Some(32),
features: " m, a".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
..Default::default()
},
}
}
1 change: 1 addition & 0 deletions src/doc/rustc/src/platform-support.md
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Expand Up @@ -339,6 339,7 @@ target | std | host | notes
`riscv32gc-unknown-linux-gnu` | | | RISC-V Linux (kernel 5.4, glibc 2.33)
`riscv32gc-unknown-linux-musl` | | | RISC-V Linux (kernel 5.4, musl 1.2.3 RISCV32 support patches)
[`riscv32im-risc0-zkvm-elf`](platform-support/riscv32im-risc0-zkvm-elf.md) | ? | | RISC Zero's zero-knowledge Virtual Machine (RV32IM ISA)
[`riscv32ima-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * | | Bare RISC-V (RV32IMA ISA)
[`riscv32imac-unknown-xous-elf`](platform-support/riscv32imac-unknown-xous-elf.md) | ? | | RISC-V Xous (RV32IMAC ISA)
[`riscv32imc-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
[`riscv32imac-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
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6 changes: 5 additions & 1 deletion src/doc/rustc/src/platform-support/riscv32-unknown-none-elf.md
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@@ -1,9 1,13 @@
# `riscv32{i,im,imc,imac,imafc}-unknown-none-elf`
# `riscv32{i,im,ima,imc,imac,imafc}-unknown-none-elf`

**Tier: 2**

Bare-metal target for RISC-V CPUs with the RV32I, RV32IM, RV32IMC, RV32IMAFC and RV32IMAC ISAs.

**Tier: 3**

Bare-metal target for RISC-V CPUs with the RV32IMA ISA.

## Target maintainers

* Rust Embedded Working Group, [RISC-V team](https://github.com/rust-embedded/wg#the-risc-v-team)
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1 change: 1 addition & 0 deletions src/tools/build-manifest/src/main.rs
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Expand Up @@ -126,6 126,7 @@ static TARGETS: &[&str] = &[
"riscv32i-unknown-none-elf",
"riscv32im-risc0-zkvm-elf",
"riscv32im-unknown-none-elf",
"riscv32ima-unknown-none-elf",
"riscv32imc-unknown-none-elf",
"riscv32imac-unknown-none-elf",
"riscv32imafc-unknown-none-elf",
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3 changes: 3 additions & 0 deletions tests/assembly/targets/targets-elf.rs
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Expand Up @@ -369,6 369,9 @@
//@ revisions: riscv32im_unknown_none_elf
//@ [riscv32im_unknown_none_elf] compile-flags: --target riscv32im-unknown-none-elf
//@ [riscv32im_unknown_none_elf] needs-llvm-components: riscv
//@ revisions: riscv32ima_unknown_none_elf
//@ [riscv32ima_unknown_none_elf] compile-flags: --target riscv32ima-unknown-none-elf
//@ [riscv32ima_unknown_none_elf] needs-llvm-components: riscv
//@ revisions: riscv32imac_esp_espidf
//@ [riscv32imac_esp_espidf] compile-flags: --target riscv32imac-esp-espidf
//@ [riscv32imac_esp_espidf] needs-llvm-components: riscv
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