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add a csky-unknown-linux-gnuabiv2 target #113658

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merged 14 commits into from
Aug 14, 2023
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add a csky-unknown-linux-gnuabiv2 target
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Dirreke committed Aug 14, 2023
commit d16409fe228f07c8a702ace7b42c1e1196ff85e6
1 change: 1 addition & 0 deletions compiler/rustc_codegen_gcc/example/alloc_system.rs
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 12,7 @@
target_arch = "mips",
target_arch = "mips32r6",
target_arch = "powerpc",
target_arch = "csky"
target_arch = "powerpc64"))]
const MIN_ALIGN: usize = 8;
#[cfg(any(target_arch = "x86_64",
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5 changes: 5 additions & 0 deletions compiler/rustc_codegen_gcc/src/asm.rs
Original file line number Diff line number Diff line change
Expand Up @@ -597,6 597,8 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => "a",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => "d",
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "d", // more specific than "r"
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::Msp430(Msp430InlineAsmRegClass::reg) => "r",
Expand Down Expand Up @@ -673,6 675,8 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => cx.type_i32(),
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => cx.type_i32(),
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::Msp430(_) => unimplemented!(),
Expand Down Expand Up @@ -860,6 864,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
InlineAsmRegClass::S390x(_) => None,
InlineAsmRegClass::Msp430(_) => None,
InlineAsmRegClass::M68k(_) => None,
InlineAsmRegClass::CSKY(_) => None,
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
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6 changes: 6 additions & 0 deletions compiler/rustc_codegen_llvm/src/asm.rs
Original file line number Diff line number Diff line change
Expand Up @@ -261,6 261,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
InlineAsmArch::M68k => {
constraints.push("~{ccr}".to_string());
}
InlineAsmArch::CSKY => {} // https://github.com/llvm/llvm-project/blob/8b76aea8d8b1b71f6220bc2845abc749f18a19b7/clang/lib/Basic/Targets/CSKY.h getClobers()
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Did you mean this as a TODO?

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No, it's finished here. just to indicate that this part of the code comes from here

}
}
if !options.contains(InlineAsmOptions::NOMEM) {
Expand Down Expand Up @@ -693,6 694,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => "a",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => "d",
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
Expand Down Expand Up @@ -792,6 795,7 @@ fn modifier_to_llvm(
bug!("LLVM backend does not support SPIR-V")
}
InlineAsmRegClass::M68k(_) => None,
InlineAsmRegClass::CSKY(_) => None,
InlineAsmRegClass::Err => unreachable!(),
}
}
Expand Down Expand Up @@ -868,6 872,8 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => cx.type_i32(),
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => cx.type_i32(),
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
Expand Down
1 change: 1 addition & 0 deletions compiler/rustc_llvm/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 12,7 @@ const OPTIONAL_COMPONENTS: &[&str] = &[
"avr",
"loongarch",
"m68k",
"csky",
"mips",
"powerpc",
"systemz",
Expand Down
7 changes: 7 additions & 0 deletions compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -105,6 105,12 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
#define SUBTARGET_M68K
#endif

#ifdef LLVM_COMPONENT_CSKY
#define SUBTARGET_CSKY SUBTARGET(CSKY)
#else
#define SUBTARGET_CSKY
#endif

#ifdef LLVM_COMPONENT_MIPS
#define SUBTARGET_MIPS SUBTARGET(Mips)
#else
Expand Down Expand Up @@ -159,6 165,7 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
SUBTARGET_AARCH64 \
SUBTARGET_AVR \
SUBTARGET_M68K \
SUBTARGET_CSKY \
SUBTARGET_MIPS \
SUBTARGET_PPC \
SUBTARGET_SYSTEMZ \
Expand Down
8 changes: 8 additions & 0 deletions compiler/rustc_llvm/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 102,14 @@ pub fn initialize_available_targets() {
LLVMInitializeM68kAsmPrinter,
LLVMInitializeM68kAsmParser
);
init_target!(
llvm_component = "csky",
LLVMInitializeCSKYTargetInfo,
LLVMInitializeCSKYTarget,
LLVMInitializeCSKYTargetMC,
LLVMInitializeCSKYAsmPrinter,
LLVMInitializeCSKYAsmParser
);
init_target!(
llvm_component = "loongarch",
LLVMInitializeLoongArchTargetInfo,
Expand Down
31 changes: 31 additions & 0 deletions compiler/rustc_target/src/abi/call/csky.rs
Original file line number Diff line number Diff line change
@@ -0,0 1,31 @@
//see https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/CSKY/CSKYCallingConv.td
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use crate::abi::call::{ArgAbi, FnAbi};

fn classify_ret<Ty>(ret: &mut ArgAbi<'_, Ty>) {
if ret.layout.is_aggregate() || ret.layout.size.bits() > 64 {
ret.make_indirect();
} else {
ret.extend_integer_width_to(32);
}
}

fn classify_arg<Ty>(arg: &mut ArgAbi<'_, Ty>) {
if arg.layout.is_aggregate() || arg.layout.size.bits() > 64 {
arg.make_indirect();
} else {
arg.extend_integer_width_to(32);
}
}

pub fn compute_abi_info<Ty>(fn_abi: &mut FnAbi<'_, Ty>) {
if !fn_abi.ret.is_ignore() {
classify_ret(&mut fn_abi.ret);
}

for arg in fn_abi.args.iter_mut() {
if arg.is_ignore() {
continue;
}
classify_arg(arg);
}
}
2 changes: 2 additions & 0 deletions compiler/rustc_target/src/abi/call/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 9,7 @@ mod amdgpu;
mod arm;
mod avr;
mod bpf;
mod csky;
mod hexagon;
mod loongarch;
mod m68k;
Expand Down Expand Up @@ -712,6 713,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {
"avr" => avr::compute_abi_info(self),
"loongarch64" => loongarch::compute_abi_info(cx, self),
"m68k" => m68k::compute_abi_info(self),
"csky" => csky::compute_abi_info(self),
"mips" | "mips32r6" => mips::compute_abi_info(cx, self),
"mips64" | "mips64r6" => mips64::compute_abi_info(cx, self),
"powerpc" => powerpc::compute_abi_info(self),
Expand Down
142 changes: 142 additions & 0 deletions compiler/rustc_target/src/asm/csky.rs
Original file line number Diff line number Diff line change
@@ -0,0 1,142 @@
use super::{InlineAsmArch, InlineAsmType};
use rustc_macros::HashStable_Generic;
use rustc_span::Symbol;
use std::fmt;

def_reg_class! {
CSKY CSKYInlineAsmRegClass {
reg,
freg,
}
}

impl CSKYInlineAsmRegClass {
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
&[]
}

pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
None
}

pub fn suggest_modifier(
self,
_arch: InlineAsmArch,
_ty: InlineAsmType,
) -> Option<(char, &'static str)> {
None
}

pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
None
}

pub fn supported_types(
self,
_arch: InlineAsmArch,
) -> &'static [(InlineAsmType, Option<Symbol>)] {
match self {
Self::reg => types! { _: I8, I16, I32, I64, F32, F64; },
Self::freg => types! { _: F32, F64; },
}
}
}

// The reserved registers are taken from <https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp#79>
def_regs! {
CSKY CSKYInlineAsmReg CSKYInlineAsmRegClass {
r0: reg = ["r0","a0"],
r1: reg = ["r1","a1"],
r2: reg = ["r2","a2"],
r3: reg = ["r3","a3"],
r4: reg = ["r4","l0"],
r5: reg = ["r5","l1"],
r6: reg = ["r6","l2"],
// r7: reg = ["r7","l3"],
// r8: reg = ["r8","l4"],
// r9: reg = ["r9","l5"],
// r10: reg = ["r10","l6"],
// r11: reg = ["r11","l7"],
// r12: reg = ["r12","t0"],
// r13: reg = ["r13","t1"],
// r14: reg = ["r14","sp"],
// r15: reg = ["r15","lr"],
// r16: reg = ["r16","l8"],
// r17: reg = ["r17","l9"],
// r18: reg = ["r18","t2"],
// r19: reg = ["r19","t3"],
// r20: reg = ["r20","t4"],
// r21: reg = ["r21","t5"],
// r22: reg = ["r22","t6"],
// r23: reg = ["r23","t7", "fp"],
// r24: reg = ["r24","t8", "sop"],
// r25: reg = ["r25","tp", "bsp"],
// r26: reg = ["r26"],
// r27: reg = ["r27"],
// r28: reg = ["r28","gb", "rgb", "rdb"],
// r29: reg = ["r29","tb", "rtb"],
// r30: reg = ["r30","svbr"],
// r31: reg = ["r31","tls"],
f0: freg = ["fr0","vr0"],
f1: freg = ["fr1","vr1"],
f2: freg = ["fr2","vr2"],
f3: freg = ["fr3","vr3"],
f4: freg = ["fr4","vr4"],
f5: freg = ["fr5","vr5"],
f6: freg = ["fr6","vr6"],
f7: freg = ["fr7","vr7"],
f8: freg = ["fr8","vr8"],
f9: freg = ["fr9","vr9"],
f10: freg = ["fr10","vr10"],
f11: freg = ["fr11","vr11"],
f12: freg = ["fr12","vr12"],
f13: freg = ["fr13","vr13"],
f14: freg = ["fr14","vr14"],
f15: freg = ["fr15","vr15"],
f16: freg = ["fr16","vr16"],
f17: freg = ["fr17","vr17"],
f18: freg = ["fr18","vr18"],
f19: freg = ["fr19","vr19"],
f20: freg = ["fr20","vr20"],
f21: freg = ["fr21","vr21"],
f22: freg = ["fr22","vr22"],
f23: freg = ["fr23","vr23"],
f24: freg = ["fr24","vr24"],
f25: freg = ["fr25","vr25"],
f26: freg = ["fr26","vr26"],
f27: freg = ["fr27","vr27"],
f28: freg = ["fr28","vr28"],
f29: freg = ["fr29","vr29"],
f30: freg = ["fr30","vr30"],
f31: freg = ["fr31","vr31"],
#error = ["r7", "l3"] =>
"the base pointer cannot be used as an operand for inline asm",
#error = ["r8","l4"] =>
"the frame pointer cannot be used as an operand for inline asm",
#error = ["r14","sp"] =>
"the stack pointer cannot be used as an operand for inline asm",
#error = ["r15","lr"] =>
"the link register cannot be used as an operand for inline asm",
#error = ["r31","tls"] =>
"reserver for tls",
#error = ["r28", "gb", "rgb", "rdb"] =>
"the global pointer cannot be used as an operand for inline asm",
#error = ["r9","l5", "r10","l6", "r11","l7", "r12","t0", "r13","t1"] =>
"reserved (no E2)",
#error = ["r16","l8", "r17","l9", "r18","t2", "r19","t3", "r20","t4", "r21","t5", "r22","t6", "r23","t7", "fp", "r24","t8", "sop", "r25","tp", "bsp"] =>
"reserved (no HighRegisters)",
#error = ["r26","r27","r29","tb", "rtb", "r30","svbr"] =>
"reserved by the ABI",
}
}

impl CSKYInlineAsmReg {
pub fn emit(
self,
out: &mut dyn fmt::Write,
_arch: InlineAsmArch,
_modifier: Option<char>,
) -> fmt::Result {
out.write_str(self.name())
}
}
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