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[core] Remove redundant MicroOpWithData bundle #392

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Sep 24, 2019
Merged

[core] Remove redundant MicroOpWithData bundle #392

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[core] Remove redundant MicroOpWithData bundle
  • Loading branch information
@jerryz123
jerryz123 committed Sep 19, 2019
commit 3b432be22eac47008ba51246febe360385c8c875
10 changes: 0 additions & 10 deletions src/main/scala/common/micro-op.scala
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Expand Up @@ -196,13 196,3 @@ object CfiType
def jalr = 3.U
}

/**
* MicroOp with data
*
* @param data_sz size of data to put with MicroOp
*/
class MicroOpWithData(val data_sz: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val data = UInt(data_sz.W)
}
1 change: 0 additions & 1 deletion src/main/scala/exu/execution-units/execution-unit.scala
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Expand Up @@ -32,7 32,6 @@ import boom.util.{ImmGen, IsKilledByBranch, BranchKillableQueue, BoomCoreStringP

/**
* Response from Execution Unit. Bundles a MicroOp with data
* TODO rename to something like MicroOpWithData
*
* @param dataWidth width of the data coming from the execution unit
*/
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2 changes: 1 addition & 1 deletion src/main/scala/exu/fp-pipeline.scala
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Expand Up @@ -43,7 43,7 @@ class FpPipeline(implicit p: Parameters) extends BoomModule with tile.HasFPUPara
// 1 for recoding.
val ll_wports = Flipped(Vec(memWidth, Decoupled(new ExeUnitResp(fLen 1))))// from memory unit
val from_int = Flipped(Decoupled(new ExeUnitResp(fLen 1)))// from integer RF
val to_sdq = Decoupled(new MicroOpWithData(fLen)) // to Load/Store Unit
val to_sdq = Decoupled(new ExeUnitResp(fLen)) // to Load/Store Unit
val to_int = Decoupled(new ExeUnitResp(xLen)) // to integer RF

val wakeups = Vec(numWakeupPorts, Valid(new ExeUnitResp(fLen 1)))
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4 changes: 2 additions & 2 deletions src/main/scala/lsu/lsu.scala
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Expand Up @@ -53,7 53,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.Str

import boom.common._
import boom.exu.{BrResolutionInfo, Exception, FuncUnitResp, CommitSignals}
import boom.exu.{BrResolutionInfo, Exception, FuncUnitResp, CommitSignals, ExeUnitResp}
import boom.util.{BoolToChar, AgePriorityEncoder, IsKilledByBranch, GetNewBrMask, WrapInc, IsOlder, UpdateBrMask}

class LSUExeIO(implicit p: Parameters) extends BoomBundle()(p)
Expand Down Expand Up @@ -116,7 116,7 @@ class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p)
val ldq_full = Output(Vec(coreWidth, Bool()))
val stq_full = Output(Vec(coreWidth, Bool()))

val fp_stdata = Flipped(Decoupled(new MicroOpWithData(fLen)))
val fp_stdata = Flipped(Decoupled(new ExeUnitResp(fLen)))

val commit = Input(new CommitSignals)
val commit_load_at_rob_head = Input(Bool())
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