-
-
Notifications
You must be signed in to change notification settings - Fork 43
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
[VHDL] Array port #195
Comments
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Currently, an array port is packed into a bit vector port.
For usability, introduce array types and use these instead of a bit vector type.
Oh. I would contribute if I would have known ruby 😄
In VHDL you need to define a whole type to be able to create array. This means you need to create a VHDL package (similar to SV package) and inside you need to define an array type for that port (or use some global defined port for all rggen ideally)
so for example in
rggen_rtl
package you can create an array typeThe above is called an unconstrained array -> it needs size provided during instantiation
and then you could define a port when generating
Originally posted by @SzymonHitachi in #194 (reply in thread)
The text was updated successfully, but these errors were encountered: