// Copyright (c) 2014-2018 ETH Zurich, University of Bologna

//

// Copyright and related rights are licensed under the Solderpad Hardware

// License, Version 0.51 (the "License"); you may not use this file except in

// compliance with the License. You may obtain a copy of the License at

// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law

// or agreed to in writing, software, hardware and materials distributed under

// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR

// CONDITIONS OF ANY KIND, either express or implied. See the License for the

// specific language governing permissions and limitations under the License.

//

// Authors:

// - Andreas Kurth <[email protected]>

// - Wolfgang Roenninger <[email protected]>

// - Fabian Schuiki <[email protected]>

// - Thomas Benz <[email protected]>

// - Matheus Cavalcante <[email protected]>

/// A set of testbench utilities for AXI interfaces.

package axi_test;

import axi_pkg::*;

/// A driver for AXI4-Lite interface.

class axi_lite_driver #(

parameter int AW = 32 ,

parameter int DW = 32 ,

parameter time TA = 0ns , // stimuli application time

parameter time TT = 0ns // stimuli test time

);

virtual AXI_LITE_DV #(

.AXI_ADDR_WIDTH(AW),

.AXI_DATA_WIDTH(DW)

) axi;

function new(

virtual AXI_LITE_DV #(

.AXI_ADDR_WIDTH(AW),

.AXI_DATA_WIDTH(DW)

) axi

);

this.axi = axi;

endfunction

function void reset_master();

axi.aw_addr <= '0;

axi.aw_prot <= '0;

axi.aw_valid <= '0;

axi.w_valid <= '0;

axi.w_data <= '0;

axi.w_strb <= '0;

axi.b_ready <= '0;

axi.ar_valid <= '0;

axi.ar_prot <= '0;

axi.ar_addr <= '0;

axi.r_ready <= '0;

endfunction

function void reset_slave();

axi.aw_ready <= '0;

axi.w_ready <= '0;

axi.b_resp <= '0;

axi.b_valid <= '0;

axi.ar_ready <= '0;

axi.r_data <= '0;

axi.r_resp <= '0;

axi.r_valid <= '0;

endfunction

task cycle_start;

#TT;

endtask

task cycle_end;

@(posedge axi.clk_i);

endtask

/// Issue a beat on the AW channel.

task send_aw (

input logic [AW-1:0] addr,

input prot_t prot

);

axi.aw_addr <= #TA addr;

axi.aw_prot <= #TA prot;

axi.aw_valid <= #TA 1;

cycle_start();

while (axi.aw_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.aw_addr <= #TA '0;

axi.aw_prot <= #TA '0;

axi.aw_valid <= #TA 0;

endtask

/// Issue a beat on the W channel.

task send_w (

input logic [DW-1:0] data,

input logic [DW/8-1:0] strb

);

axi.w_data <= #TA data;

axi.w_strb <= #TA strb;

axi.w_valid <= #TA 1;

cycle_start();

while (axi.w_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.w_data <= #TA '0;

axi.w_strb <= #TA '0;

axi.w_valid <= #TA 0;

endtask

/// Issue a beat on the B channel.

task send_b (

input axi_pkg::resp_t resp

);

axi.b_resp <= #TA resp;

axi.b_valid <= #TA 1;

cycle_start();

while (axi.b_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.b_resp <= #TA '0;

axi.b_valid <= #TA 0;

endtask

/// Issue a beat on the AR channel.

task send_ar (

input logic [AW-1:0] addr,

input prot_t prot

);

axi.ar_addr <= #TA addr;

axi.ar_prot <= #TA prot;

axi.ar_valid <= #TA 1;

cycle_start();

while (axi.ar_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.ar_addr <= #TA '0;

axi.ar_prot <= #TA '0;

axi.ar_valid <= #TA 0;

endtask

/// Issue a beat on the R channel.

task send_r (

input logic [DW-1:0] data,

input axi_pkg::resp_t resp

);

axi.r_data <= #TA data;

axi.r_resp <= #TA resp;

axi.r_valid <= #TA 1;

cycle_start();

while (axi.r_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.r_data <= #TA '0;

axi.r_resp <= #TA '0;

axi.r_valid <= #TA 0;

endtask

/// Wait for a beat on the AW channel.

task recv_aw (

output [AW-1:0] addr,

output prot_t prot

);

axi.aw_ready <= #TA 1;

cycle_start();

while (axi.aw_valid != 1) begin cycle_end(); cycle_start(); end

addr = axi.aw_addr;

prot = axi.aw_prot;

cycle_end();

axi.aw_ready <= #TA 0;

endtask

/// Wait for a beat on the W channel.

task recv_w (

output [DW-1:0] data,

output [DW/8-1:0] strb

);

axi.w_ready <= #TA 1;

cycle_start();

while (axi.w_valid != 1) begin cycle_end(); cycle_start(); end

data = axi.w_data;

strb = axi.w_strb;

cycle_end();

axi.w_ready <= #TA 0;

endtask

/// Wait for a beat on the B channel.

task recv_b (

output axi_pkg::resp_t resp

);

axi.b_ready <= #TA 1;

cycle_start();

while (axi.b_valid != 1) begin cycle_end(); cycle_start(); end

resp = axi.b_resp;

cycle_end();

axi.b_ready <= #TA 0;

endtask

/// Wait for a beat on the AR channel.

task recv_ar (

output [AW-1:0] addr,

output prot_t prot

);

axi.ar_ready <= #TA 1;

cycle_start();

while (axi.ar_valid != 1) begin cycle_end(); cycle_start(); end

addr = axi.ar_addr;

prot = axi.ar_prot;

cycle_end();

axi.ar_ready <= #TA 0;

endtask

/// Wait for a beat on the R channel.

task recv_r (

output [DW-1:0] data,

output axi_pkg::resp_t resp

);

axi.r_ready <= #TA 1;

cycle_start();

while (axi.r_valid != 1) begin cycle_end(); cycle_start(); end

data = axi.r_data;

resp = axi.r_resp;

cycle_end();

axi.r_ready <= #TA 0;

endtask

endclass

/// The data transferred on a beat on the AW/AR channels.

class axi_ax_beat #(

parameter AW = 32,

parameter IW = 8 ,

parameter UW = 1

);

rand logic [IW-1:0] ax_id = '0;

rand logic [AW-1:0] ax_addr = '0;

logic [7:0] ax_len = '0;

logic [2:0] ax_size = '0;

logic [1:0] ax_burst = '0;

logic ax_lock = '0;

logic [3:0] ax_cache = '0;

logic [2:0] ax_prot = '0;

rand logic [3:0] ax_qos = '0;

logic [3:0] ax_region = '0;

logic [5:0] ax_atop = '0; // Only defined on the AW channel.

rand logic [UW-1:0] ax_user = '0;

endclass

/// The data transferred on a beat on the W channel.

class axi_w_beat #(

parameter DW = 32,

parameter UW = 1

);

rand logic [DW-1:0] w_data = '0;

rand logic [DW/8-1:0] w_strb = '0;

logic w_last = '0;

rand logic [UW-1:0] w_user = '0;

endclass

/// The data transferred on a beat on the B channel.

class axi_b_beat #(

parameter IW = 8,

parameter UW = 1

);

rand logic [IW-1:0] b_id = '0;

axi_pkg::resp_t b_resp = '0;

rand logic [UW-1:0] b_user = '0;

endclass

/// The data transferred on a beat on the R channel.

class axi_r_beat #(

parameter DW = 32,

parameter IW = 8 ,

parameter UW = 1

);

rand logic [IW-1:0] r_id = '0;

rand logic [DW-1:0] r_data = '0;

axi_pkg::resp_t r_resp = '0;

logic r_last = '0;

rand logic [UW-1:0] r_user = '0;

endclass

/// A driver for AXI4 interface.

class axi_driver #(

parameter int AW = 32 ,

parameter int DW = 32 ,

parameter int IW = 8 ,

parameter int UW = 1 ,

parameter time TA = 0ns , // stimuli application time

parameter time TT = 0ns // stimuli test time

);

virtual AXI_BUS_DV #(

.AXI_ADDR_WIDTH(AW),

.AXI_DATA_WIDTH(DW),

.AXI_ID_WIDTH(IW),

.AXI_USER_WIDTH(UW)

) axi;

typedef axi_ax_beat #(.AW(AW), .IW(IW), .UW(UW)) ax_beat_t;

typedef axi_w_beat #(.DW(DW), .UW(UW)) w_beat_t;

typedef axi_b_beat #(.IW(IW), .UW(UW)) b_beat_t;

typedef axi_r_beat #(.DW(DW), .IW(IW), .UW(UW)) r_beat_t;

function new(

virtual AXI_BUS_DV #(

.AXI_ADDR_WIDTH(AW),

.AXI_DATA_WIDTH(DW),

.AXI_ID_WIDTH(IW),

.AXI_USER_WIDTH(UW)

) axi

);

this.axi = axi;

endfunction

function void reset_master();

axi.aw_id <= '0;

axi.aw_addr <= '0;

axi.aw_len <= '0;

axi.aw_size <= '0;

axi.aw_burst <= '0;

axi.aw_lock <= '0;

axi.aw_cache <= '0;

axi.aw_prot <= '0;

axi.aw_qos <= '0;

axi.aw_region <= '0;

axi.aw_atop <= '0;

axi.aw_user <= '0;

axi.aw_valid <= '0;

axi.w_data <= '0;

axi.w_strb <= '0;

axi.w_last <= '0;

axi.w_user <= '0;

axi.w_valid <= '0;

axi.b_ready <= '0;

axi.ar_id <= '0;

axi.ar_addr <= '0;

axi.ar_len <= '0;

axi.ar_size <= '0;

axi.ar_burst <= '0;

axi.ar_lock <= '0;

axi.ar_cache <= '0;

axi.ar_prot <= '0;

axi.ar_qos <= '0;

axi.ar_region <= '0;

axi.ar_user <= '0;

axi.ar_valid <= '0;

axi.r_ready <= '0;

endfunction

function void reset_slave();

axi.aw_ready <= '0;

axi.w_ready <= '0;

axi.b_id <= '0;

axi.b_resp <= '0;

axi.b_user <= '0;

axi.b_valid <= '0;

axi.ar_ready <= '0;

axi.r_id <= '0;

axi.r_data <= '0;

axi.r_resp <= '0;

axi.r_last <= '0;

axi.r_user <= '0;

axi.r_valid <= '0;

endfunction

task cycle_start;

#TT;

endtask

task cycle_end;

@(posedge axi.clk_i);

endtask

/// Issue a beat on the AW channel.

task send_aw (

input ax_beat_t beat

);

axi.aw_id <= #TA beat.ax_id;

axi.aw_addr <= #TA beat.ax_addr;

axi.aw_len <= #TA beat.ax_len;

axi.aw_size <= #TA beat.ax_size;

axi.aw_burst <= #TA beat.ax_burst;

axi.aw_lock <= #TA beat.ax_lock;

axi.aw_cache <= #TA beat.ax_cache;

axi.aw_prot <= #TA beat.ax_prot;

axi.aw_qos <= #TA beat.ax_qos;

axi.aw_region <= #TA beat.ax_region;

axi.aw_atop <= #TA beat.ax_atop;

axi.aw_user <= #TA beat.ax_user;

axi.aw_valid <= #TA 1;

cycle_start();

while (axi.aw_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.aw_id <= #TA '0;

axi.aw_addr <= #TA '0;

axi.aw_len <= #TA '0;

axi.aw_size <= #TA '0;

axi.aw_burst <= #TA '0;

axi.aw_lock <= #TA '0;

axi.aw_cache <= #TA '0;

axi.aw_prot <= #TA '0;

axi.aw_qos <= #TA '0;

axi.aw_region <= #TA '0;

axi.aw_atop <= #TA '0;

axi.aw_user <= #TA '0;

axi.aw_valid <= #TA 0;

endtask

/// Issue a beat on the W channel.

task send_w (

input w_beat_t beat

);

axi.w_data <= #TA beat.w_data;

axi.w_strb <= #TA beat.w_strb;

axi.w_last <= #TA beat.w_last;

axi.w_user <= #TA beat.w_user;

axi.w_valid <= #TA 1;

cycle_start();

while (axi.w_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.w_data <= #TA '0;

axi.w_strb <= #TA '0;

axi.w_last <= #TA '0;

axi.w_user <= #TA '0;

axi.w_valid <= #TA 0;

endtask

/// Issue a beat on the B channel.

task send_b (

input b_beat_t beat

);

axi.b_id <= #TA beat.b_id;

axi.b_resp <= #TA beat.b_resp;

axi.b_user <= #TA beat.b_user;

axi.b_valid <= #TA 1;

cycle_start();

while (axi.b_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.b_id <= #TA '0;

axi.b_resp <= #TA '0;

axi.b_user <= #TA '0;

axi.b_valid <= #TA 0;

endtask

/// Issue a beat on the AR channel.

task send_ar (

input ax_beat_t beat

);

axi.ar_id <= #TA beat.ax_id;

axi.ar_addr <= #TA beat.ax_addr;

axi.ar_len <= #TA beat.ax_len;

axi.ar_size <= #TA beat.ax_size;

axi.ar_burst <= #TA beat.ax_burst;

axi.ar_lock <= #TA beat.ax_lock;

axi.ar_cache <= #TA beat.ax_cache;

axi.ar_prot <= #TA beat.ax_prot;

axi.ar_qos <= #TA beat.ax_qos;

axi.ar_region <= #TA beat.ax_region;

axi.ar_user <= #TA beat.ax_user;

axi.ar_valid <= #TA 1;

cycle_start();

while (axi.ar_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.ar_id <= #TA '0;

axi.ar_addr <= #TA '0;

axi.ar_len <= #TA '0;

axi.ar_size <= #TA '0;

axi.ar_burst <= #TA '0;

axi.ar_lock <= #TA '0;

axi.ar_cache <= #TA '0;

axi.ar_prot <= #TA '0;

axi.ar_qos <= #TA '0;

axi.ar_region <= #TA '0;

axi.ar_user <= #TA '0;

axi.ar_valid <= #TA 0;

endtask

/// Issue a beat on the R channel.

task send_r (

input r_beat_t beat

);

axi.r_id <= #TA beat.r_id;

axi.r_data <= #TA beat.r_data;

axi.r_resp <= #TA beat.r_resp;

axi.r_last <= #TA beat.r_last;

axi.r_user <= #TA beat.r_user;

axi.r_valid <= #TA 1;

cycle_start();

while (axi.r_ready != 1) begin cycle_end(); cycle_start(); end

cycle_end();

axi.r_id <= #TA '0;

axi.r_data <= #TA '0;

axi.r_resp <= #TA '0;

axi.r_last <= #TA '0;

axi.r_user <= #TA '0;

axi.r_valid <= #TA 0;

endtask

/// Wait for a beat on the AW channel.

task recv_aw (

output ax_beat_t beat

);

axi.aw_ready <= #TA 1;

cycle_start();

while (axi.aw_valid != 1) begin cycle_end(); cycle_start(); end

beat = new;

beat.ax_id = axi.aw_id;

beat.ax_addr = axi.aw_addr;

beat.ax_len = axi.aw_len;

beat.ax_size = axi.aw_size;

beat.ax_burst = axi.aw_burst;

beat.ax_lock = axi.aw_lock;

beat.ax_cache = axi.aw_cache;

beat.ax_prot = axi.aw_prot;

beat.ax_qos = axi.aw_qos;

beat.ax_region = axi.aw_region;

beat.ax_atop = axi.aw_atop;

beat.ax_user = axi.aw_user;

cycle_end();

axi.aw_ready <= #TA 0;

endtask

/// Wait for a beat on the W channel.

task recv_w (

output w_beat_t beat

);

axi.w_ready <= #TA 1;

cycle_start();

while (axi.w_valid != 1) begin cycle_end(); cycle_start(); end

beat = new;

beat.w_data = axi.w_data;

beat.w_strb = axi.w_strb;

beat.w_last = axi.w_last;

beat.w_user = axi.w_user;

cycle_end();

axi.w_ready <= #TA 0;

endtask

/// Wait for a beat on the B channel.

task recv_b (

output b_beat_t beat

);

axi.b_ready <= #TA 1;

cycle_start();

while (axi.b_valid != 1) begin cycle_end(); cycle_start(); end

beat = new;

beat.b_id = axi.b_id;

beat.b_resp = axi.b_resp;

beat.b_user = axi.b_user;

cycle_end();

axi.b_ready <= #TA 0;

endtask

/// Wait for a beat on the AR channel.

task recv_ar (

output ax_beat_t beat

);

axi.ar_ready <= #TA 1;

cycle_start();

while (axi.ar_valid != 1) begin cycle_end(); cycle_start(); end

beat = new;

beat.ax_id = axi.ar_id;

beat.ax_addr = axi.ar_addr;

beat.ax_len = axi.ar_len;

beat.ax_size = axi.ar_size;

beat.ax_burst = axi.ar_burst;

beat.ax_lock = axi.ar_lock;

beat.ax_cache = axi.ar_cache;

beat.ax_prot = axi.ar_prot;

beat.ax_qos = axi.ar_qos;

beat.ax_region = axi.ar_region;

beat.ax_atop = 'X; // Not defined on the AR channel.

beat.ax_user = axi.ar_user;

cycle_end();

axi.ar_ready <= #TA 0;

endtask

/// Wait for a beat on the R channel.

task recv_r (

output r_beat_t beat

);

axi.r_ready <= #TA 1;

cycle_start();

while (axi.r_valid != 1) begin cycle_end(); cycle_start(); end

beat = new;

beat.r_id = axi.r_id;

beat.r_data = axi.r_data;

beat.r_resp = axi.r_resp;

beat.r_last = axi.r_last;

beat.r_user = axi.r_user;

cycle_end();

axi.r_ready <= #TA 0;

endtask

/// Monitor the AW channel and return the next beat.

task mon_aw (

output ax_beat_t beat

);

cycle_start();

while (!(axi.aw_valid && axi.aw_ready)) begin cycle_end(); cycle_start(); end

beat = new;

beat.ax_id = axi.aw_id;

beat.ax_addr = axi.aw_addr;

beat.ax_len = axi.aw_len;

beat.ax_size = axi.aw_size;

beat.ax_burst = axi.aw_burst;

beat.ax_lock = axi.aw_lock;

beat.ax_cache = axi.aw_cache;

beat.ax_prot = axi.aw_prot;

beat.ax_qos = axi.aw_qos;

beat.ax_region = axi.aw_region;

beat.ax_atop = axi.aw_atop;

beat.ax_user = axi.aw_user;

cycle_end();

endtask

/// Monitor the W channel and return the next beat.

task mon_w (

output w_beat_t beat

);

cycle_start();

while (!(axi.w_valid && axi.w_ready)) begin cycle_end(); cycle_start(); end

beat = new;

beat.w_data = axi.w_data;

beat.w_strb = axi.w_strb;

beat.w_last = axi.w_last;

beat.w_user = axi.w_user;

cycle_end();

endtask

/// Monitor the B channel and return the next beat.

task mon_b (

output b_beat_t beat

);

cycle_start();

while (!(axi.b_valid && axi.b_ready)) begin cycle_end(); cycle_start(); end

beat = new;

beat.b_id = axi.b_id;

beat.b_resp = axi.b_resp;

beat.b_user = axi.b_user;

cycle_end();

endtask

/// Monitor the AR channel and return the next beat.

task mon_ar (

output ax_beat_t beat

);

cycle_start();

while (!(axi.ar_valid && axi.ar_ready)) begin cycle_end(); cycle_start(); end

beat = new;

beat.ax_id = axi.ar_id;

beat.ax_addr = axi.ar_addr;

beat.ax_len = axi.ar_len;

beat.ax_size = axi.ar_size;

beat.ax_burst = axi.ar_burst;

beat.ax_lock = axi.ar_lock;

beat.ax_cache = axi.ar_cache;

beat.ax_prot = axi.ar_prot;

beat.ax_qos = axi.ar_qos;

beat.ax_region = axi.ar_region;

beat.ax_atop = 'X; // Not defined on the AR channel.

beat.ax_user = axi.ar_user;

cycle_end();

endtask

/// Monitor the R channel and return the next beat.

task mon_r (

output r_beat_t beat

);

cycle_start();

while (!(axi.r_valid && axi.r_ready)) begin cycle_end(); cycle_start(); end

beat = new;

beat.r_id = axi.r_id;

beat.r_data = axi.r_data;

beat.r_resp = axi.r_resp;

beat.r_last = axi.r_last;

beat.r_user = axi.r_user;

cycle_end();

endtask

endclass

class axi_rand_master #(

// AXI interface parameters

parameter int AW = 32,

parameter int DW = 32,

parameter int IW = 8,

parameter int UW = 1,

// Stimuli application and test time

parameter time TA = 0ps,

parameter time TT = 0ps,

// Maximum number of read and write transactions in flight

parameter int MAX_READ_TXNS = 1,

parameter int MAX_WRITE_TXNS = 1,

// Upper and lower bounds on wait cycles on Ax, W, and resp (R and B) channels

parameter int AX_MIN_WAIT_CYCLES = 0,

parameter int AX_MAX_WAIT_CYCLES = 100,

parameter int W_MIN_WAIT_CYCLES = 0,

parameter int W_MAX_WAIT_CYCLES = 5,

parameter int RESP_MIN_WAIT_CYCLES = 0,

parameter int RESP_MAX_WAIT_CYCLES = 20,

// AXI feature usage

parameter int SIZE_ALIGN = 0,

parameter int AXI_MAX_BURST_LEN = 0, // maximum number of beats in burst; 0 = AXI max (256)

parameter int TRAFFIC_SHAPING = 0,

parameter bit AXI_EXCLS = 1'b0,

parameter bit AXI_ATOPS = 1'b0,

parameter bit AXI_BURST_FIXED = 1'b1,

parameter bit AXI_BURST_INCR = 1'b1,

parameter bit AXI_BURST_WRAP = 1'b0,

parameter bit UNIQUE_IDS = 1'b0, // guarantee that the ID of each transaction is

// unique among all in-flight transactions in the

// same direction

// Dependent parameters, do not override.

parameter int AXI_STRB_WIDTH = DW/8,

parameter int N_AXI_IDS = 2**IW

);

typedef axi_test::axi_driver #(

.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TA), .TT(TT)

) axi_driver_t;

typedef logic [AW-1:0] addr_t;

typedef axi_pkg::burst_t burst_t;

typedef axi_pkg::cache_t cache_t;

typedef logic [DW-1:0] data_t;

typedef logic [IW-1:0] id_t;

typedef axi_pkg::len_t len_t;

typedef axi_pkg::size_t size_t;

typedef logic [UW-1:0] user_t;

typedef axi_pkg::mem_type_t mem_type_t;

typedef axi_driver_t::ax_beat_t ax_beat_t;

typedef axi_driver_t::b_beat_t b_beat_t;

typedef axi_driver_t::r_beat_t r_beat_t;

typedef axi_driver_t::w_beat_t w_beat_t;

static addr_t PFN_MASK = '{11: 1'b0, 10: 1'b0, 9: 1'b0, 8: 1'b0, 7: 1'b0, 6: 1'b0, 5: 1'b0,

4: 1'b0, 3: 1'b0, 2: 1'b0, 1: 1'b0, 0: 1'b0, default: '1};

axi_driver_t drv;

int unsigned r_flight_cnt[N_AXI_IDS-1:0],

w_flight_cnt[N_AXI_IDS-1:0],

tot_r_flight_cnt,

tot_w_flight_cnt;

logic [N_AXI_IDS-1:0] atop_resp_b,

atop_resp_r;

len_t max_len;

burst_t allowed_bursts[$];

semaphore cnt_sem;

ax_beat_t aw_queue[$],

w_queue[$],

excl_queue[$];

typedef struct packed {

addr_t addr_begin;

addr_t addr_end;

mem_type_t mem_type;

} mem_region_t;

mem_region_t mem_map[$];

struct packed {

int unsigned len ;

int unsigned size ;

int unsigned cprob;

} traffic_shape[$];

int unsigned max_cprob;

function new(

virtual AXI_BUS_DV #(

.AXI_ADDR_WIDTH(AW),

.AXI_DATA_WIDTH(DW),

.AXI_ID_WIDTH(IW),

.AXI_USER_WIDTH(UW)

) axi

);

if (AXI_MAX_BURST_LEN <= 0 || AXI_MAX_BURST_LEN > 256) begin

this.max_len = 255;

end else begin

this.max_len = AXI_MAX_BURST_LEN - 1;

end

this.drv = new(axi);

this.cnt_sem = new(1);

this.reset();

if (AXI_BURST_FIXED) begin

this.allowed_bursts.push_back(BURST_FIXED);

end

if (AXI_BURST_INCR) begin

this.allowed_bursts.push_back(BURST_INCR);

end

if (AXI_BURST_WRAP) begin

this.allowed_bursts.push_back(BURST_WRAP);

end

assert(allowed_bursts.size()) else $fatal(1, "At least one burst type has to be specified!");

endfunction

function void reset();

drv.reset_master();

r_flight_cnt = '{default: 0};

w_flight_cnt = '{default: 0};

tot_r_flight_cnt = 0;

tot_w_flight_cnt = 0;

atop_resp_b = '0;

atop_resp_r = '0;

endfunction

function void add_memory_region(input addr_t addr_begin, input addr_t addr_end, input mem_type_t mem_type);

mem_map.push_back({addr_begin, addr_end, mem_type});

endfunction

function void clear_memory_regions();

mem_map.delete();

endfunction

function void add_traffic_shaping(input int unsigned len, input int unsigned freq);

int unsigned size = -1;

if (traffic_shape.size() == 0)

traffic_shape.push_back({len, size, freq});

else

traffic_shape.push_back({len, size, traffic_shape[$].cprob freq});

max_cprob = traffic_shape[$].cprob;

endfunction : add_traffic_shaping

function void add_traffic_shaping_with_size(input int unsigned len, input int unsigned size, input int unsigned freq);

if (traffic_shape.size() == 0)

traffic_shape.push_back({len, size, freq});

else

traffic_shape.push_back({len, size, traffic_shape[$].cprob freq});

max_cprob = traffic_shape[$].cprob;

endfunction : add_traffic_shaping_with_size

function ax_beat_t new_rand_burst(input logic is_read);

automatic logic rand_success;

automatic ax_beat_t ax_beat = new;

automatic addr_t addr;

automatic burst_t burst;

automatic cache_t cache;

automatic id_t id;

automatic qos_t qos;

automatic len_t len;

automatic size_t size;

automatic int unsigned mem_region_idx;

automatic mem_region_t mem_region;

automatic int cprob;

// No memory regions defined

if (mem_map.size() == 0) begin

// Return a dummy region

mem_region = '{

addr_begin: '0,

addr_end: '1,

mem_type: axi_pkg::NORMAL_NONCACHEABLE_BUFFERABLE

};

end else begin

// Randomly pick a memory region

rand_success = std::randomize(mem_region_idx) with {

mem_region_idx < mem_map.size();

}; assert(rand_success);

mem_region = mem_map[mem_region_idx];

end

// Randomly pick burst type.

rand_success = std::randomize(burst) with {

burst inside {this.allowed_bursts};

}; assert(rand_success);

ax_beat.ax_burst = burst;

// Determine memory type.

ax_beat.ax_cache = is_read ? axi_pkg::get_arcache(mem_region.mem_type) : axi_pkg::get_awcache(mem_region.mem_type);

// Randomize beat size.

if (TRAFFIC_SHAPING) begin

rand_success = std::randomize(cprob) with {

cprob >= 0; cprob < max_cprob;

}; assert(rand_success);

for (int i = 0; i < traffic_shape.size(); i )

if (traffic_shape[i].cprob > cprob) begin

len = traffic_shape[i].len;

size = traffic_shape[i].size;

if (ax_beat.ax_burst == BURST_WRAP) begin

assert (len inside {len_t'(1), len_t'(3), len_t'(7), len_t'(15)});

end

break;

end

// Randomize address. Make sure that the burst does not cross a 4KiB boundary.

forever begin

if(size==-1) begin

rand_success = std::randomize(size) with {

2**size <= AXI_STRB_WIDTH;

2**size <= len;

}; assert(rand_success);

ax_beat.ax_size = size;

ax_beat.ax_len = ((len (1 << size) - 1) >> size) - 1;

end else begin

ax_beat.ax_size = size;

ax_beat.ax_len = len;

end

rand_success = std::randomize(addr) with {

addr >= mem_region.addr_begin;

addr <= mem_region.addr_end;

addr len <= mem_region.addr_end;

}; assert(rand_success);

if (axi_pkg::beat_addr(addr, ax_beat.ax_size, ax_beat.ax_len, ax_beat.ax_burst, 0) >> 12 ==

axi_pkg::beat_addr(addr, ax_beat.ax_size, ax_beat.ax_len, ax_beat.ax_burst, ax_beat.ax_len) >> 12) begin

break;

end

end

end else begin

// Randomize address. Make sure that the burst does not cross a 4KiB boundary.

forever begin

// Randomize burst length.

rand_success = std::randomize(len) with {

len <= this.max_len;

(ax_beat.ax_burst == BURST_WRAP) ->

len inside {len_t'(1), len_t'(3), len_t'(7), len_t'(15)};

}; assert(rand_success);

rand_success = std::randomize(size) with {

2**size <= AXI_STRB_WIDTH;

}; assert(rand_success);

ax_beat.ax_size = size;

ax_beat.ax_len = len;

// Randomize address

rand_success = std::randomize(addr) with {

addr >= mem_region.addr_begin;

addr <= mem_region.addr_end;

addr ((len 1) << size) <= mem_region.addr_end;

}; assert(rand_success);

if (axi_pkg::beat_addr(addr, ax_beat.ax_size, ax_beat.ax_len, ax_beat.ax_burst, 0) >> 12 ==

axi_pkg::beat_addr(addr, ax_beat.ax_size, ax_beat.ax_len, ax_beat.ax_burst, ax_beat.ax_len) >> 12) begin

break;

end

end

end

ax_beat.ax_addr = axi_pkg::aligned_addr(addr, axi_pkg::size_t'(SIZE_ALIGN) );

rand_success = std::randomize(id); assert(rand_success);

rand_success = std::randomize(qos); assert(rand_success);

// The random ID *must* be legalized with `legalize_id()` before the beat is sent! This is

// currently done in the functions `create_aws()` and `send_ars()`.

ax_beat.ax_id = id;

ax_beat.ax_qos = qos;

return ax_beat;

endfunction

task rand_atop_burst(inout ax_beat_t beat);

automatic logic rand_success;

forever begin

beat.ax_atop[5:4] = $random();

if (beat.ax_atop[5:4] != 2'b00 && !AXI_BURST_INCR) begin

// We can emit ATOPs only if INCR bursts are allowed.

$warning("ATOP suppressed because INCR bursts are disabled!");

beat.ax_atop[5:4] = 2'b00;

end

if (beat.ax_atop[5:4] != 2'b00) begin // ATOP

// Determine `ax_atop`.

if (beat.ax_atop[5:4] == axi_pkg::ATOP_ATOMICSTORE ||

beat.ax_atop[5:4] == axi_pkg::ATOP_ATOMICLOAD) begin

// Endianness

beat.ax_atop[3] = $random();

// Atomic operation

beat.ax_atop[2:0] = $random();

end else begin // Atomic{Swap,Compare}

beat.ax_atop[3:1] = '0;

beat.ax_atop[0] = $random();

end

// Determine `ax_size` and `ax_len`.

if (2**beat.ax_size < AXI_STRB_WIDTH) begin

// Transaction does *not* occupy full data bus, so we must send just one beat. [E1.1.3]

beat.ax_len = '0;

end else begin

automatic int unsigned bytes;

if (beat.ax_atop == axi_pkg::ATOP_ATOMICCMP) begin

// Total data transferred in burst can be 2, 4, 8, 16, or 32 B.

automatic int unsigned log_bytes;

rand_success = std::randomize(log_bytes) with {

log_bytes > 0; 2**log_bytes <= 32;

}; assert(rand_success);

bytes = 2**log_bytes;

end else begin

// Total data transferred in burst can be 1, 2, 4, or 8 B.

if (AXI_STRB_WIDTH >= 8) begin

bytes = AXI_STRB_WIDTH;

end else begin

automatic int unsigned log_bytes;

rand_success = std::randomize(log_bytes); assert(rand_success);

log_bytes = log_bytes % (4 - $clog2(AXI_STRB_WIDTH)) - $clog2(AXI_STRB_WIDTH);

bytes = 2**log_bytes;

end

end

beat.ax_len = bytes / AXI_STRB_WIDTH - 1;

end

// Determine `ax_addr` and `ax_burst`.

if (beat.ax_atop == axi_pkg::ATOP_ATOMICCMP) begin