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pwr.h (g0, g4, l4) provide access to the PWR_PUCRx and PWR_PDCRx registers by defining PWR_PORT_[A-G] and applying an offset with PWR_PUCR() and PWR_PDCR() macros.
This appears to be due to nesting the MMIO32 macro. It seems the right pattern would be to remove the MMIO32 macro from the PWR_PORT_[A-G] definitions, aping the the GPIO pattern where the GPIO_PORT_x_BASE are integer constants that are wrapped by MMIO32 in the downstream macros designed to work with these constants.
I've confirmed this solution works, but I'm too underwater to open a PR myself, and haven't investigated potential side effects / dependencies / references. Documenting the issue in case anyone else runs into it, if anything else.
The text was updated successfully, but these errors were encountered:
Background
pwr.h (g0, g4, l4) provide access to the PWR_PUCRx and PWR_PDCRx registers by defining PWR_PORT_[A-G] and applying an offset with PWR_PUCR() and PWR_PDCR() macros.
libopencm3/include/libopencm3/stm32/g4/pwr.h
Line 68 in b8e6e5d
Issue
I can neither make assignments nor copy-modify-write using this macro. The following both fail, for various combinations of port and right hand side:
Solution
This appears to be due to nesting the MMIO32 macro. It seems the right pattern would be to remove the MMIO32 macro from the PWR_PORT_[A-G] definitions, aping the the GPIO pattern where the GPIO_PORT_x_BASE are integer constants that are wrapped by MMIO32 in the downstream macros designed to work with these constants.
I've confirmed this solution works, but I'm too underwater to open a PR myself, and haven't investigated potential side effects / dependencies / references. Documenting the issue in case anyone else runs into it, if anything else.
The text was updated successfully, but these errors were encountered: