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ibex
ibex PublicForked from lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog
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cv32e40p
cv32e40p PublicForked from openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog
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tech_cells_generic
tech_cells_generic PublicForked from pulp-platform/tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
SystemVerilog 1
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L2_tcdm_hybrid_interco
L2_tcdm_hybrid_interco PublicForked from pulp-platform/L2_tcdm_hybrid_interco
SystemVerilog