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  1. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog

  2. cv32e40p cv32e40p Public

    Forked from openhwgroup/cv32e40p

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog

  3. pulp_soc pulp_soc Public

    Forked from pulp-platform/pulp_soc

    SystemVerilog

  4. tech_cells_generic tech_cells_generic Public

    Forked from pulp-platform/tech_cells_generic

    Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

    SystemVerilog 1

  5. scm scm Public

    Forked from pulp-platform/scm

    SystemVerilog

  6. L2_tcdm_hybrid_interco L2_tcdm_hybrid_interco Public

    Forked from pulp-platform/L2_tcdm_hybrid_interco

    SystemVerilog

Contribution activity

January 2025

jsailer has no activity yet for this period.
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