Notes, codes and resources for the course Computer Organisation and Architecture, IIT Kharagpur

You can find the MIPS notes in the MIPS folder

Check in the Verilog folder. Algorithm and illustration for booth multiplier is added in the Booth Multiplier folder

The CPU is designed based on a reduced instruction set, programmed using verilog and implemented in single cycle mode. Documentation and notes can be found in the verilog folder.