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Add ability to configure build and sim arguments at connection time
enhancement
New feature or request
#26
opened Feb 28, 2023 by
mkorbel1
Resolve race condition in RohdConnector during interactive debug and SV timeout
bug
Something isn't working
#15
opened Feb 8, 2023 by
mkorbel1
Add testing that SV New feature or request
#
delays are properly handled
enhancement
#13
opened Feb 8, 2023 by
mkorbel1
Add more extensive testing that New feature or request
throwOnUnexpectedEnd
works with PortConfig
enhancement
#12
opened Feb 8, 2023 by
mkorbel1
Add a New feature or request
good first issue
Good for newcomers
PortConfig
test where the process crashes before Simulator.run
enhancement
#11
opened Feb 8, 2023 by
mkorbel1
Properly Something isn't working
await
the Simulator.reset
in finish_test.dart
bug
#10
opened Feb 8, 2023 by
mkorbel1
Don't send more ticks than necessary
enhancement
New feature or request
#8
opened Feb 8, 2023 by
mkorbel1
Add a test covering scenarios with multiple SV simulator ticks per timestamp
enhancement
New feature or request
#7
opened Feb 8, 2023 by
mkorbel1
Add testing for clock-divider logic with cosimulation
enhancement
New feature or request
#6
opened Feb 7, 2023 by
mkorbel1
Listeners linger after simulations end
bug
Something isn't working
#5
opened Feb 7, 2023 by
mkorbel1
Add more types of arguments for New feature or request
Cosim
Module
s
enhancement
#4
opened Feb 7, 2023 by
mkorbel1
Build an annotation-based cosim-wrapper code generator
enhancement
New feature or request
#3
opened Feb 7, 2023 by
mkorbel1
Enable cosim access to hierarchically reference signals in SystemVerilog modules and submodules
enhancement
New feature or request
#2
opened Feb 7, 2023 by
mkorbel1
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