C standards drafts

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

RISC-V RV32IMAFC Core for MCU

辛苦三星期，造台计算机！

Sifive All Aboard 系列文章翻译

The official repository for the gem5 computer-system architecture simulator.

Modeling Architectural Platform

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

Collect some CS textbooks for learning.

Collect some IC textbooks for learning.

数字IC相关资料

The batteries-included testing and formal verification library for Chisel-based RTL designs.

Python - 100天从新手到大师

清华大学操作系统课程实验 (OS Kernel Labs)

💻深度学习实战：手写数字识别、Discuz验证码识别、垃圾分类、语义分割

Xv6 for RISC-V

Open-source high-performance RISC-V processor

龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）

24 Game Solver: gives you all dissimilar solutions

My code and life.