For more information and updates: http://alexforencich.com/wiki/en/verilog/pcie/start

GitHub repository: https://github.com/alexforencich/verilog-pcie

Collection of PCI express related components. Includes PCIe to AXI and AXI lite bridges and a flexible, high-performance DMA subsystem. Currently supports operation with several FPGA families from Xilinx and Intel. Includes full cocotb testbenches that utilize cocotbext-pcie and cocotbext-axi.

Example designs are included for the following FPGA boards:

• Alpha Data ADM-PCIE-9V3 (Xilinx Virtex UltraScale XCVU3P)
• BittWare 520N-MX (Intel Stratix 10 MX 1SM21CHU2F53E2VG)
• Exablaze ExaNIC X10 (Xilinx Kintex UltraScale XCKU035)
• Exablaze ExaNIC X25 (Xilinx Kintex UltraScale XCKU3P)
• Silicom fb2CG@KU15P (Xilinx Kintex UltraScale XCKU15P)
• Intel Stratix 10 DX dev kit (Intel Stratix 10 MX 1SD280PT2F55E1VG)
• Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 1SM21CHU1F53E1VG)
• Terasic DE10-Agilex (Intel Agilex F AGFB014R24B2E2V)
• Xilinx Alveo U50 (Xilinx Virtex UltraScale XCU50)
• Xilinx Alveo U55C (Xilinx Virtex UltraScale XCU55C)
• Xilinx Alveo U55N/Varium C1100 (Xilinx Virtex UltraScale XCU55N)
• Xilinx Alveo U200 (Xilinx Virtex UltraScale XCU200)
• Xilinx Alveo U250 (Xilinx Virtex UltraScale XCU250)
• Xilinx Alveo U280 (Xilinx Virtex UltraScale XCU280)
• Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
• Xilinx VCU118 (Xilinx Virtex UltraScale XCVU9P)
• Xilinx VCU1525 (Xilinx Virtex UltraScale XCVU9P)
• Xilinx ZCU106 (Xilinx Zynq UltraScale XCZU7EV)

The PCIe modules use a generic, FPGA-independent interface for handling PCIe TLPs. This permits the same core logic to be used on multiple FPGA families, with interface shims to connect to the PCIe IP on each target device.

The pcie_us_if module is an adaptation shim for Xilinx 7-series, UltraScale, and UltraScale . It handles the main datapath, configuration space parameters, MSI interrupts, and flow control.

The pcie_s10_if module is an adaptation shim for Intel Stratix 10 GX/SX/TX/MX series FPGAs that use the H-Tile or L-Tile for PCIe. It handles the main datapath, configuration space parameters, MSI interrupts, and flow control.

The pcie_ptile_if module is an adaptation shim for Intel Stratix 10 DX/Agilex series FPGAs that use the P-Tile for PCIe. It handles the main datapath, configuration space parameters, and flow control.

The pcie_axi_master, pcie_axil_master, and pcie_axil_master_minimal modules provide a bridge between PCIe and AXI. These can be used to implement PCIe BARs.

The pcie_axil_master_minimal module is a very simple module for providing register access, supporting only 32 bit operations.

The pcie_axi_master module is more complex, converting PCIe operations to AXI bursts. It can be used to terminate device-to-device DMA operations with reasonable performance.

The pcie_tlp_demux_bar module can be used to demultiplex PCIe operations based on the target BAR.

The split DMA interface/DMA client modules support highly flexible, highly performant DMA operations. The DMA interface and DMA client modules are connected by dual port RAMs with a high performance segmented memory interface. The segmented memory interface is a better 'impedance match' to the PCIe hard core interface - data realignment can be done in the same clock cycle; no bursts, address decoding, arbitration, or reordering simplifies implementation and provides much higher performance than AXI. The architecture is also quite flexible as it decouples the DMA interface from the clients with dual port RAMs, enabling mixing different client interface types and widths and even supporting clients running in different clock domains without datapath FIFOs.

The dma_if_pcie module connects a generic, FPGA-independent PCIe interface to the segmented memory interface.

The dma_if_axi module connects an AXI interface to the segmented memory interface.

The dma_psdpram module is a dual clock, parallel simple dual port RAM module with a segmented interface. The depth is independently adjustable from the address width, simplifying use of the segmented interface. The module also contains a parametrizable output pipeline register to improve timing.

The dma_if_mux module enables sharing the DMA interface across several DMA clients. This module handles the tags and select lines appropriately on both the descriptor and segmented memory interface for plug-and-play operation without address assignment - routing is completely determined by component connections. The module also contains a FIFO to maintain read data ordering across multiple clients. Make sure to equalize pipeline delay across all paths for maximum performance.

DMA client modules connect the segmented memory interface to different internal interfaces.

The dma_client_axis_source and dma_client_axis_sink modules provide support for streaming DMA over AXI stream. The AXI stream width can be any power of two fraction of the segmented memory interface width.

General-purpose parametrizable arbiter. Supports priority and round-robin arbitration. Supports blocking until request release or acknowledge.

Frame-aware AXI stream arbitrated multiplexer with parametrizable data width and port count. Supports priority and round-robin arbitration.

AXI stream sink DMA client module. Uses a segmented memory interface.

AXI stream source DMA client module. Uses a segmented memory interface.

AXI DMA interface module. Parametrizable interface width. Uses a double width segmented memory interface.

AXI DMA interface module. Parametrizable interface width. Uses a double width segmented memory interface.

AXI DMA interface module. Parametrizable interface width. Uses a double width segmented memory interface.

DMA interface descriptor mux module. Enables sharing a DMA interface module between multiple DMA client modules.

DMA interface mux module. Enables sharing a DMA interface module between multiple DMA client modules. Wrapper for dma_if_mux_rd and dma_if_mux_wr.

DMA interface mux module. Enables sharing a DMA interface module between multiple DMA client modules. Wrapper for dma_if_desc_mux and dma_ram_demux_wr.

DMA interface mux module. Enables sharing a DMA interface module between multiple DMA client modules. Wrapper for dma_if_desc_mux and dma_ram_demux_rd.

PCIe DMA interface module. Parametrizable interface width. Uses a double width segmented memory interface.

PCIe DMA interface module. Parametrizable interface width. Uses a double width segmented memory interface.

PCIe DMA interface module. Parametrizable interface width. Uses a double width segmented memory interface.

PCIe DMA interface module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Uses a double width segmented memory interface. Wrapper for dma_if_pcie_us_rd and dma_if_pcie_us_wr.

PCIe DMA interface module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Uses a double width segmented memory interface.

PCIe DMA interface module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Uses a double width segmented memory interface.

DMA RAM module. Segmented simple dual port RAM to connect a DMA interface module to a DMA client.

DMA RAM module with asynchronous clocks. Segmented simple dual port RAM to connect a DMA interface module to a DMA client.

DMA RAM interface demultiplexer module. Wrapper for dma_ram_demux_rd and dma_ram_demux_wr.

DMA RAM interface demultiplexer module for read operations.

DMA RAM interface demultiplexer module for write operations.

Descriptor multiplexer/demultiplexer for PCIe AXI DMA module. Enables sharing the PCIe AXI DMA module between multiple request sources, interleaving requests and distributing responses.

PCIe AXI master module. Parametrizable interface width and AXI burst length. Wrapper for pcie_axi_master_rd and pcie_axi_master_wr.

PCIe AXI master module. Parametrizable interface width and AXI burst length.

PCIe AXI master module. Parametrizable interface width and AXI burst length.

PCIe AXI lite master module. Parametrizable interface width.

Minimal PCIe AXI lite master module. Parametrizable interface width. Only supports aligned 32-bit operations, all other operations will result in a completer abort. Only supports 32-bit AXI lite.

MSI-X support module. Implements MSI-X table and pending bit array with AXI lite register interface, accepts interrupt requests on a streaming interface, and generates corresponding write request TLPs.

Configuration shim for Intel Stratix 10 DX/Agilex series FPGAs (P-Tile).

PCIe interface shim for Intel Stratix 10 DX/Agilex series FPGAs (P-Tile). Wrapper for all Intel Stratix 10 DX/Agilex PCIe interface shims.

PCIe interface shim (RX) for Intel Stratix 10 DX/Agilex series FPGAs (P-Tile).

PCIe interface shim (TX) for Intel Stratix 10 DX/Agilex series FPGAs (P-Tile).

Configuration shim for Intel Stratix 10 GX/SX/TX/MX series FPGAs (H-Tile/L-Tile).

PCIe interface shim for Intel Stratix 10 GX/SX/TX/MX series FPGAs (H-Tile/L-Tile). Wrapper for all Intel Stratix 10 GX/SX/TX/MX PCIe interface shims.

PCIe interface shim (RX) for Intel Stratix 10 GX/SX/TX/MX series FPGAs (H-Tile/L-Tile).

PCIe interface shim (TX) for Intel Stratix 10 GX/SX/TX/MX series FPGAs (H-Tile/L-Tile).

MSI shim for Intel Stratix 10 GX/SX/TX/MX series FPGAs (H-Tile/L-Tile).

PCIe TLP demultiplexer module.

PCIe TLP demultiplexer module. Wrapper for pcie_tlp_demux with parametrizable BAR ID matching logic.

PCIe TLP FIFO module.

PCIe TLP FIFO module with raw non-destriped output.

PCIe TLP FIFO multiplexer module.

PCIe TLP multiplexer module.

PCIe AXI DMA module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length. Wrapper for pcie_us_axi_dma_rd and pcie_us_axi_dma_wr.

PCIe AXI DMA module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length.

PCIe AXI DMA module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length.

PCIe AXI master module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length. Wrapper for pcie_us_axi_master_rd and pcie_us_axi_master_wr.

PCIe AXI master module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length.

PCIe AXI master module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length.

PCIe AXI lite master module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit PCIe interfaces.

Demux module for Xilinx UltraScale CQ interface. Can be used to route incoming requests based on function, BAR, and other fields. Supports 64, 128, 256, and 512 bit datapaths.

Demux module for Xilinx UltraScale RC interface. Can be used to route incoming completions based on the requester ID (function). Supports 64, 128, 256, and 512 bit datapaths.

Configuration shim for Xilinx UltraScale series FPGAs.

PCIe interface shim for Xilinx UltraScale series FPGAs. Wrapper for all Xilinx UltraScale PCIe interface shims.

PCIe interface shim (CC) for Xilinx UltraScale series FPGAs.

PCIe interface shim (CQ) for Xilinx UltraScale series FPGAs.

PCIe interface shim (RC) for Xilinx UltraScale series FPGAs.

PCIe interface shim (RQ) for Xilinx UltraScale series FPGAs.

MSI shim for Xilinx UltraScale series FPGAs.

Parametrizable priority encoder.

Parametrizable pulse merge module. Combines several single-cycle pulse status signals together.

arbiter.v                  : Parametrizable arbiter
axis_arb_mux.v             : Parametrizable AXI stream mux
dma_client_axis_sink.v     : AXI stream sink DMA client
dma_client_axis_source.v   : AXI stream source DMA client
dma_if_axi.v               : AXI DMA interface
dma_if_axi_rd.v            : AXI DMA interface (read)
dma_if_axi_wr.v            : AXI DMA interface (write)
dma_if_desc_mux.v          : DMA interface descriptor mux
dma_if_mux.v               : DMA interface mux
dma_if_mux_rd.v            : DMA interface mux (read)
dma_if_mux_wr.v            : DMA interface mux (write)
dma_if_pcie.v              : PCIe DMA interface
dma_if_pcie_rd.v           : PCIe DMA interface (read)
dma_if_pcie_wr.v           : PCIe DMA interface (write)
dma_if_pcie_us.v           : PCIe DMA interface for Xilinx UltraScale
dma_if_pcie_us_rd.v        : PCIe DMA interface for Xilinx UltraScale (read)
dma_if_pcie_us_wr.v        : PCIe DMA interface for Xilinx UltraScale (write)
dma_psdpram.v              : DMA RAM (segmented simple dual port RAM)
dma_psdpram_async.v        : DMA RAM (segmented simple dual port RAM)
dma_ram_demux.v            : DMA RAM demultiplexer
dma_ram_demux_rd.v         : DMA RAM demultiplexer (read)
dma_ram_demux_wr.v         : DMA RAM demultiplexer (write)
pcie_axi_dma_desc_mux.v    : Descriptor mux for DMA engine
pcie_axi_master.v          : PCIe AXI master module
pcie_axi_master_rd.v       : PCIe AXI master read module
pcie_axi_master_wr.v       : PCIe AXI master write module
pcie_axil_master.v         : PCIe AXI Lite master module
pcie_axil_master_minimal.v : PCIe AXI Lite master module (minimal)
pcie_msix.v                : PCIe MSI-X support module
pcie_ptile_cfg.v           : Configuration shim for Intel P-Tile
pcie_ptile_if.v            : PCIe interface shim (Intel P-Tile)
pcie_ptile_if_rx.v         : PCIe interface shim (RX) (Intel P-Tile)
pcie_ptile_if_tx.v         : PCIe interface shim (TX) (Intel P-Tile)
pcie_s10_cfg.v             : Configuration shim for Intel Stratix 10
pcie_s10_if.v              : PCIe interface shim (Intel Stratix 10)
pcie_s10_if_rx.v           : PCIe interface shim (RX) (Intel Stratix 10)
pcie_s10_if_tx.v           : PCIe interface shim (TX) (Intel Stratix 10)
pcie_s10_msi.v             : MSI shim for Intel Stratix 10 devices
pcie_tlp_demux.v           : PCIe TLP demultiplexer
pcie_tlp_demux_bar.v       : PCIe TLP demultiplexer (BAR ID)
pcie_tlp_fifo.v            : PCIe TLP FIFO
pcie_tlp_fifo_raw.v        : PCIe TLP FIFO (raw output)
pcie_tlp_fifo_mux.v        : PCIe TLP FIFO   multiplexer
pcie_tlp_mux.v             : PCIe TLP multiplexer
pcie_us_axi_dma.v          : PCIe AXI DMA module (Xilinx UltraScale)
pcie_us_axi_dma_rd.v       : PCIe AXI DMA read module (Xilinx UltraScale)
pcie_us_axi_dma_wr.v       : PCIe AXI DMA write module (Xilinx UltraScale)
pcie_us_axi_master.v       : PCIe AXI master module (Xilinx UltraScale)
pcie_us_axi_master_rd.v    : PCIe AXI master read module (Xilinx UltraScale)
pcie_us_axi_master_wr.v    : PCIe AXI master write module (Xilinx UltraScale)
pcie_us_axil_master.v      : PCIe AXI Lite master module (Xilinx UltraScale)
pcie_us_axis_cq_demux.v    : Parametrizable AXI stream CQ demux
pcie_us_axis_rc_demux.v    : Parametrizable AXI stream RC demux
pcie_us_cfg.v              : Configuration shim for Xilinx UltraScale devices
pcie_us_if.v               : PCIe interface shim (Xilinx UltraScale)
pcie_us_if_cc.v            : PCIe interface shim (CC) (Xilinx UltraScale)
pcie_us_if_cq.v            : PCIe interface shim (CQ) (Xilinx UltraScale)
pcie_us_if_rc.v            : PCIe interface shim (RC) (Xilinx UltraScale)
pcie_us_if_rq.v            : PCIe interface shim (RQ) (Xilinx UltraScale)
pcie_us_msi.v              : MSI shim for Xilinx UltraScale devices
priority_encoder.v         : Parametrizable priority encoder
pulse_merge                : Parametrizable pulse merge module

Running the included testbenches requires cocotb, cocotbext-axi, cocotbext-pcie, and Icarus Verilog. The testbenches can be run with pytest directly (requires cocotb-test), pytest via tox, or via cocotb makefiles.