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Move bridge init/finish handling into the simulation base #1441

Merged
merged 1 commit into from
Feb 28, 2023
Merged

Move bridge init/finish handling into the simulation base #1441

merged 1 commit into from
Feb 28, 2023

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nandor
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@nandor nandor commented Feb 27, 2023 •
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Bridge initialisation/finalisation is now consistent across all tests and has a better-defined place in the lifetime of a simulation.

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UI / API Impact

Verilog / AGFI Compatibility

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  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
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@nandor nandor added the changelog:omit Do not include this PR in the changelog label Feb 27, 2023
@nandor nandor force-pushed the widget-cleanup branch 4 times, most recently from 9ec994f to b504d45 Compare February 28, 2023 17:24
Base automatically changed from widget-cleanup to main February 28, 2023 19:47
@nandor nandor enabled auto-merge (squash) February 28, 2023 20:17
@nandor
Move bridge init/finish handling into the simulation base
6c2a8b3 
The changes exposed a problem in the `AXI4Buffer` done signal. To avoid relying on latencies,
the done signal is now gated with reset.
@nandor nandor merged commit c7dbbe2 into main Feb 28, 2023
@nandor nandor deleted the init-finish branch February 28, 2023 23:44
@abejgonzalez abejgonzalez mentioned this pull request Mar 6, 2023
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@davidbiancolin davidbiancolin davidbiancolin approved these changes

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@nandor @davidbiancolin