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Verilog AXI stream components for FPGA implementation
FPGA implementation of Chinese SM4 encryption algorithm.
a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier
Xilinx PCIe to MIG DDR4 example designs and custom part data files
FPGA-based GZIP (deflate) compressor. Input raw data and output standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据,输出标准的GZIP格式,即常见的 .gz / .tar.gz 文件的格式。
Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
A implement of Chinese SHA(SM3) on FPGA from SHU ACTION team
lists of most popular repositories for most favoured programming languages (according to StackOverflow)
lock-free FIFO queue by C native built it, easy built cross platform(no extra dependencies needed) , guarantee thread safety memory management ever!
It's a robust lockless queue used in multiprocessing, and it can deal with the situation that any process aborts at any line.
Must-have verilog systemverilog modules
verilog implement of SM4 encryption algorithm
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)
Description of Chinese SM3 Hash algorithm with Verilog HDL