🔍 Zoomable Waveform viewer for the Web

(System)Verilog to Chisel translator

Digital Design with Chisel

Network on Chip Implementation written in SytemVerilog

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

Converts a VCD file to a Chisel tester input file

SoftFloat release 3

Yosys Open SYnthesis Suite

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

Simple RISC-V 3-stage Pipeline in Chisel

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Hammer: Highly Agile Masks Made Effortlessly from RTL

A Library of Chisel3 Tools for Digital Signal Processing

A coverage library for Chisel designs

Chisel Cheatsheet

A scala based simulator for circuits described by a LoFirrtl file

RISC-VのCPU作った

SystemVerilog language server client for Visual Studio Code

SystemVerilog linter

SystemVerilog parser library fully compliant with IEEE 1800-2017

SystemVerilog language server

A tiny header-only C library for Sixel.

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

Working Draft of the RISC-V Debug Specification Standard

RISC-V port of newlib

RISCV Rust Toolchain