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e6809.c
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e6809.c
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/* From VecX : Valavan Manohararajah */
#include <stdio.h>
#include "e6809.h"
/* code assumptions:
* - it is assumed that an 'int' is at least 16 bits long.
* - a 16-bit register has valid bits only in the lower 16 bits and an
* 8-bit register has valid bits only in the lower 8 bits. the upper
* may contain garbage!
* - all reading functions are assumed to return the requested data in
* the lower bits with the unused upper bits all set to zero.
*/
#define einline __inline
enum {
FLAG_E = 0x80,
FLAG_F = 0x40,
FLAG_H = 0x20,
FLAG_I = 0x10,
FLAG_N = 0x08,
FLAG_Z = 0x04,
FLAG_V = 0x02,
FLAG_C = 0x01,
IRQ_NORMAL = 0,
IRQ_SYNC = 1,
IRQ_CWAI = 2
};
/* index registers */
static unsigned reg_x;
static unsigned reg_y;
/* user stack pointer */
static unsigned reg_u;
/* hardware stack pointer */
static unsigned reg_s;
/* program counter */
static unsigned reg_pc;
/* accumulators */
static unsigned reg_a;
static unsigned reg_b;
/* direct page register */
static unsigned reg_dp;
/* condition codes */
static unsigned reg_cc;
/* flag to see if interrupts should be handled (sync/cwai). */
static unsigned irq_status;
static unsigned *rptr_xyus[4] = {
®_x,
®_y,
®_u,
®_s
};
static unsigned trace_cpu;
/* user defined read and write functions */
unsigned char e6809_read8(unsigned address);
void e6809_write8(unsigned address, unsigned char data);
/* obtain a particular condition code. returns 0 or 1. */
static einline unsigned get_cc (unsigned flag)
{
return (reg_cc / flag) & 1;
}
/* set a particular condition code to either 0 or 1.
* value parameter must be either 0 or 1.
*/
static einline void set_cc (unsigned flag, unsigned value)
{
reg_cc &= ~flag;
reg_cc |= value * flag;
}
/* test carry */
static einline unsigned test_c (unsigned i0, unsigned i1,
unsigned r, unsigned sub)
{
unsigned flag;
flag = (i0 | i1) & ~r; /* one of the inputs is 1 and output is 0 */
flag |= (i0 & i1); /* both inputs are 1 */
flag = (flag >> 7) & 1;
flag ^= sub; /* on a sub, carry is opposite the carry of an add */
return flag;
}
/* test negative */
static einline unsigned test_n (unsigned r)
{
return (r >> 7) & 1;
}
/* test for zero in lower 8 bits */
static einline unsigned test_z8 (unsigned r)
{
unsigned flag;
flag = ~r;
flag = (flag >> 4) & (flag & 0xf);
flag = (flag >> 2) & (flag & 0x3);
flag = (flag >> 1) & (flag & 0x1);
return flag;
}
/* test for zero in lower 16 bits */
static einline unsigned test_z16 (unsigned r)
{
unsigned flag;
flag = ~r;
flag = (flag >> 8) & (flag & 0xff);
flag = (flag >> 4) & (flag & 0xf);
flag = (flag >> 2) & (flag & 0x3);
flag = (flag >> 1) & (flag & 0x1);
return flag;
}
/* overflow is set whenever the sign bits of the inputs are the same
* but the sign bit of the result is not same as the sign bits of the
* inputs.
*/
static einline unsigned test_v (unsigned i0, unsigned i1, unsigned r)
{
unsigned flag;
flag = ~(i0 ^ i1); /* input sign bits are the same */
flag &= (i0 ^ r); /* input sign and output sign not same */
flag = (flag >> 7) & 1;
return flag;
}
static einline unsigned get_reg_d (void)
{
return (reg_a << 8) | (reg_b & 0xff);
}
static einline void set_reg_d (unsigned value)
{
reg_a = value >> 8;
reg_b = value;
}
/* read a byte ... the returned value has the lower 8-bits set to the byte
* while the upper bits are all zero.
*/
static einline unsigned read8 (unsigned address)
{
return e6809_read8(address & 0xffff);
}
/* write a byte ... only the lower 8-bits of the unsigned data
* is written. the upper bits are ignored.
*/
static einline void write8 (unsigned address, unsigned data)
{
e6809_write8(address & 0xffff, (unsigned char) data);
}
static einline unsigned read16 (unsigned address)
{
unsigned datahi, datalo;
datahi = read8 (address);
datalo = read8 (address 1);
return (datahi << 8) | datalo;
}
static einline void write16 (unsigned address, unsigned data)
{
write8 (address, data >> 8);
write8 (address 1, data);
}
static einline void push8 (unsigned *sp, unsigned data)
{
(*sp)--;
write8 (*sp, data);
}
static einline unsigned pull8 (unsigned *sp)
{
unsigned data;
data = read8 (*sp);
(*sp) ;
return data;
}
static einline void push16 (unsigned *sp, unsigned data)
{
push8 (sp, data);
push8 (sp, data >> 8);
}
static einline unsigned pull16 (unsigned *sp)
{
unsigned datahi, datalo;
datahi = pull8 (sp);
datalo = pull8 (sp);
return (datahi << 8) | datalo;
}
/* read a byte from the address pointed to by the pc */
static einline unsigned pc_read8 (void)
{
unsigned data;
data = read8 (reg_pc);
reg_pc ;
return data;
}
/* read a word from the address pointed to by the pc */
static einline unsigned pc_read16 (void)
{
unsigned data;
data = read16 (reg_pc);
reg_pc = 2;
return data;
}
/* sign extend an 8-bit quantity into a 16-bit quantity */
static einline unsigned sign_extend (unsigned data)
{
return (~(data & 0x80) 1) | (data & 0xff);
}
/* direct addressing, upper byte of the address comes from
* the direct page register, and the lower byte comes from the
* instruction itself.
*/
static einline unsigned ea_direct (void)
{
return (reg_dp << 8) | pc_read8 ();
}
/* extended addressing, address is obtained from 2 bytes following
* the instruction.
*/
static einline unsigned ea_extended (void)
{
return pc_read16 ();
}
/* indexed addressing */
static einline unsigned ea_indexed (unsigned *cycles)
{
unsigned r, op, ea;
/* post byte */
op = pc_read8 ();
r = (op >> 5) & 3;
switch (op) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x05: case 0x06: case 0x07:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
case 0x20: case 0x21: case 0x22: case 0x23:
case 0x24: case 0x25: case 0x26: case 0x27:
case 0x28: case 0x29: case 0x2a: case 0x2b:
case 0x2c: case 0x2d: case 0x2e: case 0x2f:
case 0x40: case 0x41: case 0x42: case 0x43:
case 0x44: case 0x45: case 0x46: case 0x47:
case 0x48: case 0x49: case 0x4a: case 0x4b:
case 0x4c: case 0x4d: case 0x4e: case 0x4f:
case 0x60: case 0x61: case 0x62: case 0x63:
case 0x64: case 0x65: case 0x66: case 0x67:
case 0x68: case 0x69: case 0x6a: case 0x6b:
case 0x6c: case 0x6d: case 0x6e: case 0x6f:
/* R, [0, 15] */
ea = *rptr_xyus[r] (op & 0xf);
(*cycles) ;
break;
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1a: case 0x1b:
case 0x1c: case 0x1d: case 0x1e: case 0x1f:
case 0x30: case 0x31: case 0x32: case 0x33:
case 0x34: case 0x35: case 0x36: case 0x37:
case 0x38: case 0x39: case 0x3a: case 0x3b:
case 0x3c: case 0x3d: case 0x3e: case 0x3f:
case 0x50: case 0x51: case 0x52: case 0x53:
case 0x54: case 0x55: case 0x56: case 0x57:
case 0x58: case 0x59: case 0x5a: case 0x5b:
case 0x5c: case 0x5d: case 0x5e: case 0x5f:
case 0x70: case 0x71: case 0x72: case 0x73:
case 0x74: case 0x75: case 0x76: case 0x77:
case 0x78: case 0x79: case 0x7a: case 0x7b:
case 0x7c: case 0x7d: case 0x7e: case 0x7f:
/* R, [-16, -1] */
ea = *rptr_xyus[r] (op & 0xf) - 0x10;
(*cycles) ;
break;
case 0x80: case 0x81:
case 0xa0: case 0xa1:
case 0xc0: case 0xc1:
case 0xe0: case 0xe1:
/* ,R / ,R */
ea = *rptr_xyus[r];
*rptr_xyus[r] = 1 (op & 1);
*cycles = 2 (op & 1);
break;
case 0x90: case 0x91:
case 0xb0: case 0xb1:
case 0xd0: case 0xd1:
case 0xf0: case 0xf1:
/* [,R ] ??? / [,R ] */
ea = read16 (*rptr_xyus[r]);
*rptr_xyus[r] = 1 (op & 1);
*cycles = 5 (op & 1);
break;
case 0x82: case 0x83:
case 0xa2: case 0xa3:
case 0xc2: case 0xc3:
case 0xe2: case 0xe3:
/* ,-R / ,--R */
*rptr_xyus[r] -= 1 (op & 1);
ea = *rptr_xyus[r];
*cycles = 2 (op & 1);
break;
case 0x92: case 0x93:
case 0xb2: case 0xb3:
case 0xd2: case 0xd3:
case 0xf2: case 0xf3:
/* [,-R] ??? / [,--R] */
*rptr_xyus[r] -= 1 (op & 1);
ea = read16 (*rptr_xyus[r]);
*cycles = 5 (op & 1);
break;
case 0x84: case 0xa4:
case 0xc4: case 0xe4:
/* ,R */
ea = *rptr_xyus[r];
break;
case 0x94: case 0xb4:
case 0xd4: case 0xf4:
/* [,R] */
ea = read16 (*rptr_xyus[r]);
*cycles = 3;
break;
case 0x85: case 0xa5:
case 0xc5: case 0xe5:
/* B,R */
ea = *rptr_xyus[r] sign_extend (reg_b);
*cycles = 1;
break;
case 0x95: case 0xb5:
case 0xd5: case 0xf5:
/* [B,R] */
ea = read16 (*rptr_xyus[r] sign_extend (reg_b));
*cycles = 4;
break;
case 0x86: case 0xa6:
case 0xc6: case 0xe6:
/* A,R */
ea = *rptr_xyus[r] sign_extend (reg_a);
*cycles = 1;
break;
case 0x96: case 0xb6:
case 0xd6: case 0xf6:
/* [A,R] */
ea = read16 (*rptr_xyus[r] sign_extend (reg_a));
*cycles = 4;
break;
case 0x88: case 0xa8:
case 0xc8: case 0xe8:
/* byte,R */
ea = *rptr_xyus[r] sign_extend (pc_read8 ());
*cycles = 1;
break;
case 0x98: case 0xb8:
case 0xd8: case 0xf8:
/* [byte,R] */
ea = read16 (*rptr_xyus[r] sign_extend (pc_read8 ()));
*cycles = 4;
break;
case 0x89: case 0xa9:
case 0xc9: case 0xe9:
/* word,R */
ea = *rptr_xyus[r] pc_read16 ();
*cycles = 4;
break;
case 0x99: case 0xb9:
case 0xd9: case 0xf9:
/* [word,R] */
ea = read16 (*rptr_xyus[r] pc_read16 ());
*cycles = 7;
break;
case 0x8b: case 0xab:
case 0xcb: case 0xeb:
/* D,R */
ea = *rptr_xyus[r] get_reg_d ();
*cycles = 4;
break;
case 0x9b: case 0xbb:
case 0xdb: case 0xfb:
/* [D,R] */
ea = read16 (*rptr_xyus[r] get_reg_d ());
*cycles = 7;
break;
case 0x8c: case 0xac:
case 0xcc: case 0xec:
/* byte, PC */
r = sign_extend (pc_read8 ());
ea = reg_pc r;
*cycles = 1;
break;
case 0x9c: case 0xbc:
case 0xdc: case 0xfc:
/* [byte, PC] */
r = sign_extend (pc_read8 ());
ea = read16 (reg_pc r);
*cycles = 4;
break;
case 0x8d: case 0xad:
case 0xcd: case 0xed:
/* word, PC */
r = pc_read16 ();
ea = reg_pc r;
*cycles = 5;
break;
case 0x9d: case 0xbd:
case 0xdd: case 0xfd:
/* [word, PC] */
r = pc_read16 ();
ea = read16 (reg_pc r);
*cycles = 8;
break;
case 0x9f:
/* [address] */
ea = read16 (pc_read16 ());
*cycles = 5;
break;
default:
printf ("undefined post-byte\n");
break;
}
return ea;
}
/* instruction: neg
* essentially (0 - data).
*/
static einline unsigned inst_neg (unsigned data)
{
unsigned i0, i1, r;
i0 = 0;
i1 = ~data;
r = i0 i1 1;
set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0));
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, test_v (i0, i1, r));
set_cc (FLAG_C, test_c (i0, i1, r, 1));
return r;
}
/* instruction: com */
static einline unsigned inst_com (unsigned data)
{
unsigned r;
r = ~data;
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, 0);
set_cc (FLAG_C, 1);
return r;
}
/* instruction: lsr
* cannot be faked as an add or substract.
*/
static einline unsigned inst_lsr (unsigned data)
{
unsigned r;
r = (data >> 1) & 0x7f;
set_cc (FLAG_N, 0);
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_C, data & 1);
return r;
}
/* instruction: ror
* cannot be faked as an add or substract.
*/
static einline unsigned inst_ror (unsigned data)
{
unsigned r, c;
c = get_cc (FLAG_C);
r = ((data >> 1) & 0x7f) | (c << 7);
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_C, data & 1);
return r;
}
/* instruction: asr
* cannot be faked as an add or substract.
*/
static einline unsigned inst_asr (unsigned data)
{
unsigned r;
r = ((data >> 1) & 0x7f) | (data & 0x80);
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_C, data & 1);
return r;
}
/* instruction: asl
* essentially (data data). simple addition.
*/
static einline unsigned inst_asl (unsigned data)
{
unsigned i0, i1, r;
i0 = data;
i1 = data;
r = i0 i1;
set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0));
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, test_v (i0, i1, r));
set_cc (FLAG_C, test_c (i0, i1, r, 0));
return r;
}
/* instruction: rol
* essentially (data data carry). addition with carry.
*/
static einline unsigned inst_rol (unsigned data)
{
unsigned i0, i1, c, r;
i0 = data;
i1 = data;
c = get_cc (FLAG_C);
r = i0 i1 c;
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, test_v (i0, i1, r));
set_cc (FLAG_C, test_c (i0, i1, r, 0));
return r;
}
/* instruction: dec
* essentially (data - 1).
*/
static einline unsigned inst_dec (unsigned data)
{
unsigned i0, i1, r;
i0 = data;
i1 = 0xff;
r = i0 i1;
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, test_v (i0, i1, r));
return r;
}
/* instruction: inc
* essentially (data 1).
*/
static einline unsigned inst_inc (unsigned data)
{
unsigned i0, i1, r;
i0 = data;
i1 = 1;
r = i0 i1;
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, test_v (i0, i1, r));
return r;
}
/* instruction: tst */
static einline void inst_tst8 (unsigned data)
{
set_cc (FLAG_N, test_n (data));
set_cc (FLAG_Z, test_z8 (data));
set_cc (FLAG_V, 0);
}
static einline void inst_tst16 (unsigned data)
{
set_cc (FLAG_N, test_n (data >> 8));
set_cc (FLAG_Z, test_z16 (data));
set_cc (FLAG_V, 0);
}
/* instruction: clr */
static einline void inst_clr (void)
{
set_cc (FLAG_N, 0);
set_cc (FLAG_Z, 1);
set_cc (FLAG_V, 0);
set_cc (FLAG_C, 0);
}
/* instruction: suba/subb */
static einline unsigned inst_sub8 (unsigned data0, unsigned data1)
{
unsigned i0, i1, r;
i0 = data0;
i1 = ~data1;
r = i0 i1 1;
set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0));
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, test_v (i0, i1, r));
set_cc (FLAG_C, test_c (i0, i1, r, 1));
return r;
}
/* instruction: sbca/sbcb/cmpa/cmpb.
* only 8-bit version, 16-bit version not needed.
*/
static einline unsigned inst_sbc (unsigned data0, unsigned data1)
{
unsigned i0, i1, c, r;
i0 = data0;
i1 = ~data1;
c = 1 - get_cc (FLAG_C);
r = i0 i1 c;
set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0));
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, test_v (i0, i1, r));
set_cc (FLAG_C, test_c (i0, i1, r, 1));
return r;
}
/* instruction: anda/andb/bita/bitb.
* only 8-bit version, 16-bit version not needed.
*/
static einline unsigned inst_and (unsigned data0, unsigned data1)
{
unsigned r;
r = data0 & data1;
inst_tst8 (r);
return r;
}
/* instruction: eora/eorb.
* only 8-bit version, 16-bit version not needed.
*/
static einline unsigned inst_eor (unsigned data0, unsigned data1)
{
unsigned r;
r = data0 ^ data1;
inst_tst8 (r);
return r;
}
/* instruction: adca/adcb
* only 8-bit version, 16-bit version not needed.
*/
static einline unsigned inst_adc (unsigned data0, unsigned data1)
{
unsigned i0, i1, c, r;
i0 = data0;
i1 = data1;
c = get_cc (FLAG_C);
r = i0 i1 c;
set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0));
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, test_v (i0, i1, r));
set_cc (FLAG_C, test_c (i0, i1, r, 0));
return r;
}
/* instruction: ora/orb.
* only 8-bit version, 16-bit version not needed.
*/
static einline unsigned inst_or (unsigned data0, unsigned data1)
{
unsigned r;
r = data0 | data1;
inst_tst8 (r);
return r;
}
/* instruction: adda/addb */
static einline unsigned inst_add8 (unsigned data0, unsigned data1)
{
unsigned i0, i1, r;
i0 = data0;
i1 = data1;
r = i0 i1;
set_cc (FLAG_H, test_c (i0 << 4, i1 << 4, r << 4, 0));
set_cc (FLAG_N, test_n (r));
set_cc (FLAG_Z, test_z8 (r));
set_cc (FLAG_V, test_v (i0, i1, r));
set_cc (FLAG_C, test_c (i0, i1, r, 0));
return r;
}
/* instruction: addd */
static einline unsigned inst_add16 (unsigned data0, unsigned data1)
{
unsigned i0, i1, r;
i0 = data0;
i1 = data1;
r = i0 i1;
set_cc (FLAG_N, test_n (r >> 8));
set_cc (FLAG_Z, test_z16 (r));
set_cc (FLAG_V, test_v (i0 >> 8, i1 >> 8, r >> 8));
set_cc (FLAG_C, test_c (i0 >> 8, i1 >> 8, r >> 8, 0));
return r;
}
/* instruction: subd */
static einline unsigned inst_sub16 (unsigned data0, unsigned data1)
{
unsigned i0, i1, r;
i0 = data0;
i1 = ~data1;
r = i0 i1 1;
set_cc (FLAG_N, test_n (r >> 8));
set_cc (FLAG_Z, test_z16 (r));
set_cc (FLAG_V, test_v (i0 >> 8, i1 >> 8, r >> 8));
set_cc (FLAG_C, test_c (i0 >> 8, i1 >> 8, r >> 8, 1));
return r;
}
/* instruction: 8-bit offset branch */
static einline void inst_bra8 (unsigned test, unsigned op, unsigned *cycles)
{
unsigned offset, mask;
offset = pc_read8 ();
/* trying to avoid an if statement */
mask = (test ^ (op & 1)) - 1; /* 0xffff when taken, 0 when not taken */
reg_pc = sign_extend (offset) & mask;
*cycles = 3;
}
/* instruction: 16-bit offset branch */
static einline void inst_bra16 (unsigned test, unsigned op, unsigned *cycles)
{
unsigned offset, mask;
offset = pc_read16 ();
/* trying to avoid an if statement */
mask = (test ^ (op & 1)) - 1; /* 0xffff when taken, 0 when not taken */
reg_pc = offset & mask;
*cycles = 5 - mask;
}
/* instruction: pshs/pshu */
static einline void inst_psh (unsigned op, unsigned *sp,
unsigned data, unsigned *cycles)
{
if (op & 0x80) {
push16 (sp, reg_pc);
*cycles = 2;
}
if (op & 0x40) {
/* either s or u */
push16 (sp, data);
*cycles = 2;
}
if (op & 0x20) {
push16 (sp, reg_y);
*cycles = 2;
}
if (op & 0x10) {
push16 (sp, reg_x);
*cycles = 2;
}
if (op & 0x08) {
push8 (sp, reg_dp);
*cycles = 1;
}
if (op & 0x04) {
push8 (sp, reg_b);
*cycles = 1;
}
if (op & 0x02) {
push8 (sp, reg_a);
*cycles = 1;
}
if (op & 0x01) {
push8 (sp, reg_cc);
*cycles = 1;
}
}
/* instruction: puls/pulu */
static einline void inst_pul (unsigned op, unsigned *sp, unsigned *osp,
unsigned *cycles)
{
if (op & 0x01) {
reg_cc = pull8 (sp);
*cycles = 1;
}
if (op & 0x02) {
reg_a = pull8 (sp);
*cycles = 1;
}
if (op & 0x04) {
reg_b = pull8 (sp);
*cycles = 1;
}
if (op & 0x08) {
reg_dp = pull8 (sp);
*cycles = 1;
}
if (op & 0x10) {
reg_x = pull16 (sp);
*cycles = 2;
}
if (op & 0x20) {
reg_y = pull16 (sp);
*cycles = 2;
}
if (op & 0x40) {
/* either s or u */
*osp = pull16 (sp);
*cycles = 2;
}
if (op & 0x80) {
reg_pc = pull16 (sp);
*cycles = 2;
}
}
static einline unsigned exgtfr_read (unsigned reg)
{