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BrianHG-DDR3-Controller
BrianHG-DDR3-Controller PublicForked from DECAfpga/BrianHG-DDR3-Controller
DDR3 Controller, 16 read, 16 write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included.
SystemVerilog 2
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OpenROAD-example
OpenROAD-example PublicForked from helloworld1983/OpenROAD-example
Hello World
Verilog 1
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deca-mandelbrot
deca-mandelbrot PublicForked from amaranth-farm/fpga-mandelbrot
The Terasic DECA board as a mandelbrot acceleerator
Python 1
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tang_nano_9k_test
tang_nano_9k_test PublicLiteX Tang nano 9K run under Windows powershell/WSL
Python 1
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