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STM32F103

This repository contains my libraries to use STM32F103C8T6 peripherals. It is written in C and uses Eclipse OpenOCD STLink-V2 to debug the bluepill board. It depends on stdPeriph libraries.

Bluepill specifications

  • STM32F103C8T6 microcontroller (ARM Cortex-M3)
  • 72MHz
  • Flash: 64/128 KB
  • SRAM: 20 KB
  • 3 x General purpose 1 x Advanced control timers
  • 2 x SPI
  • 2 x I2C
  • 3 x USART
  • 1 x USB
  • 1 x CAN
  • 37 x GPIO
  • 2 x ADC / 10 channels (12 bits)
  • LQFP48 / UFQFPN48 package
  • Little endian LSB first

Bluepill pinout

Memory and bus architecture

Clock domains for each peripheral:

Bus architecture

DMA channels for each peripheral:

DMA request mapping DMA request mapping

Project configurations

Configure inc and src folder
Project > Properties > C/C   General > Path and Symbols > Includes > GNU C  

Project > Properties > C/C   General > Path and Symbols > Source Location
OpenOCD Configurations
Debug Configurations > GDB OpenOCD Debbuging > Debugger > Config Options:

-f /usr/share/openocd/scripts/board/bluepill.cfg
-f interface/stlink-v2.cfg 
Putty command (Debugging via UART)
  • Baud rate = 9600 (user defined)
  • Data bit = 8
  • Stop bits = 1
  • Parity = None
  • Flow control = None
sudo putty /dev/ttyUSB0 -serial -sercfg 9600,8,n,1,N

Third-Party

FatFS (SDCard using SPI)

FreeRTOS

Drivers

  • clock.h
  • rtc.h
  • timer.h
  • uart.h
  • adc.h

Clock

Clock sources (SYSCLK): - HSI Oscillator Clock - HSE Oscillator Clock - PLL Clock Secondary clock sources? - LSI RC (40kHz) - LSE crystal (32.768kHz)

  • AHB and APB2 operates at full speeed (72MHz)
  • APB1 is limited to 36MHz

Clock configuration

  • Current function only sets to 72MHz

RTC

Clock sources (RTCCLK):

- HSE/128 (62.5KHz)
- LSE clock (32.768kHz)
- LSI clock (40KHz)
  • Current functions supports LSE as source
  • Wrong time zone configuration

POWER

Low power modes: * Sleep * Standby * Stop

TIMER

  • Advanced control timers (TIM1 and TIM8)
    • 16 bit auto-reload counter
  • General-purpose timers (TIM2 to TIM5)

ADC

  • 12 bits
  • Up to 18 multiplexed channels (16 external, 2 internal sources)
  • Data alignment (ADC->CR2 |= ALIGN)
  • The ADC input clock is synchonous with APB2 clock and it must not exceed 14MHz
  • Regular (up to 16 conversions) or injected (up to 4 conversions) groups
  • Single (CONT = 0) or continuous (CONT = 1) conversion mode
  • Calibration (ADC->CR2 |= CAL)

To Do:

  • Clock configuration
    • Configure other clock speeds
    • Modify while HSE RDY
  • RTC: Wrong time zone configuration
  • Modify Delay for TIMx (instead of only TIM4)
  • Add ADCx channels (only working for channels 0 and 6)
  • Error Handling (enum Error_Type inside each class)
  • Rewrite SD library

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