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  1. avsdbgp_3v3 avsdbgp_3v3 Public

    This repository will keep the simulation files, steps and other relevant files in the development of Bandgap Reference IP for the EICT IITG-VSD summer online research internship 2020.

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  2. intern_poweranalysis_TCL intern_poweranalysis_TCL Public

    Forked from yalamanchilivahini5/vsdtclpowertool

    The aim of this project is to create an open source power analysis tool using TCL for estimating average switching power and leakage power.

    Tcl

  3. Viterbi-Algorithm Viterbi-Algorithm Public

    Forked from Archit-halder/Viterbi-Algorithm

    This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.

    Verilog

  4. vsdsram vsdsram Public

    Forked from yash-k99/vsdsram

    Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM

  5. avsdadc_3v3 avsdadc_3v3 Public

    Forked from ADC-TEAM2020/avsdadc_3v3

    This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online Internship 2020 by the ADC Team.

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  6. SCL-EICT-Internship SCL-EICT-Internship Public

    This Repository will keep the simulation files, outputs and other relevant files used in the SCL Chandigarh and EICT Academy, IIT Guwahati Online Internship for VLSI Circuit Design.

    Verilog