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Single pipeline AES 128 bit encryption using S-box as Look up table.
Online judge server for Verilog | verilogoj.ustc.edu.cn
A List of Free and Open Source Hardware Verification Tools and Frameworks
A lightweight server clone of Amazon S3 that simulates most of the commands supported by S3 with minimal dependencies
Macros in Python: quasiquotes, case classes, LINQ and more!
🌊 Digital timing diagram rendering engine
Python packages providing a library for Verification Stimulus and Coverage
Random instruction generator for RISC-V processor verification
A random instruction generator for the RISCV architecture for testing purposes
aneels3 / cocotb
Forked from cocotb/cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
training labs and examples
In case you want to contribute, ping on https://gitter.im/NITSkmOS/algo.
Checkstyle is a development tool to help programmers write Java code that adheres to a coding standard. By default it supports the Google Java Style Guide and Sun Code Conventions, but is highly co…