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Single pipeline AES 128 bit encryption using S-box as Look up table.

Verilog 4 3 Updated Jul 13, 2018

D3.js based wave (signal) visualizer

TypeScript 58 8 Updated Jan 22, 2024

100 Days of RTL

SystemVerilog 326 97 Updated Aug 15, 2024

QT-based viewer for UCIS coverage data

Python 7 2 Updated Jul 7, 2022
Python 1 Updated Aug 6, 2021

Online judge server for Verilog | verilogoj.ustc.edu.cn

Vue 75 12 Updated Jun 25, 2024

A List of Free and Open Source Hardware Verification Tools and Frameworks

482 46 Updated Sep 8, 2023

A lightweight server clone of Amazon S3 that simulates most of the commands supported by S3 with minimal dependencies

Ruby 2,941 355 Updated Apr 13, 2023

Macros in Python: quasiquotes, case classes, LINQ and more!

TSQL 3,275 176 Updated Jun 10, 2023

🌊 Digital timing diagram rendering engine

JavaScript 2,936 363 Updated Apr 2, 2024

Python packages providing a library for Verification Stimulus and Coverage

Python 112 26 Updated Sep 22, 2024

Random instruction generator for RISC-V processor verification

Python 1,004 322 Updated Aug 29, 2024

A random instruction generator for the RISCV architecture for testing purposes

Python 5 3 Updated Apr 3, 2017

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Python 1 Updated Apr 11, 2020

Algorithm

Python 5 84 Updated Oct 28, 2021

training labs and examples

SystemVerilog 397 173 Updated Aug 1, 2022

In case you want to contribute, ping on https://gitter.im/NITSkmOS/algo.

C 99 302 Updated Nov 1, 2020

A beginner snake game made with python2

Python 4 1 Updated Mar 29, 2018

Checkstyle is a development tool to help programmers write Java code that adheres to a coding standard. By default it supports the Google Java Style Guide and Sun Code Conventions, but is highly co…

Java 8,306 3,664 Updated Sep 28, 2024
Verilog 1 Updated Jan 3, 2018

HDL libraries and projects

Verilog 1,494 1,506 Updated Sep 27, 2024