I'm Anil Sharma, a Verification Engineer from India. Graduated from NIT SIKKIM, former Hardware Intern @IIT Bombay
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Intel
- Bengaluru, India
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chipsalliance/riscv-dv
chipsalliance/riscv-dv PublicRandom instruction generator for RISC-V processor verification
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verible
verible PublicForked from chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
C
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pyvsc
pyvsc PublicForked from fvutils/pyvsc
Python packages providing a library for Verification Stimulus and Coverage
Python
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