Skip to content
View aneels3's full-sized avatar
:octocat:
:octocat:
13 followers · 5 following
  • Intel
  • Bengaluru, India

Achievements

Achievement: Pull Sharkx2Achievement: Arctic Code Vault Contributor

Achievements

Achievement: Pull Sharkx2Achievement: Arctic Code Vault Contributor
Block or Report

Block or report aneels3

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
aneels3/README.md

Hi there 👋

I'm Anil Sharma, a Verification Engineer from India. Graduated from NIT SIKKIM, former Hardware Intern @IIT Bombay

📈 My GitHub Stats

Anil's

Anil Sharma | Twitter Anil's LinkdeIN Anil's HackerRank

Pinned Loading

  1. aneels3.github.io aneels3.github.io Public

    CSS

  2. AES-128 AES-128 Public

    Single pipeline AES 128 bit encryption using S-box as Look up table.

    Verilog 4 3

  3. chipsalliance/riscv-dv chipsalliance/riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 988 321

  4. verible verible Public

    Forked from chipsalliance/verible

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

    C

  5. pyvsc pyvsc Public

    Forked from fvutils/pyvsc

    Python packages providing a library for Verification Stimulus and Coverage

    Python