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ERROR: Can't open ABC output file.
pending-verification
This issue is pending verification and/or reproduction
#4522
opened Aug 5, 2024 by
exhaust-create
Synchronous-read memory recognized as asynchronous
pending-verification
This issue is pending verification and/or reproduction
#4521
opened Aug 5, 2024 by
gzz2000
Support quoted strings as arguments to passes
feature-request
#4511
opened Jul 26, 2024 by
gussmith23
Autoname seems to get stuck in a loop and consume all the memory on the system
pending-verification
This issue is pending verification and/or reproduction
#4509
opened Jul 25, 2024 by
QuantamHD
Add support/workaround for flattening
inout
port with tri-state signals
feature-request
#4501
opened Jul 21, 2024 by
Rodrigodd
Custom Yosys Passes Result in Faulty Synthesis and Simulation Errors
pending-verification
This issue is pending verification and/or reproduction
#4491
opened Jul 15, 2024 by
LoSyTe
ABC: execution of command failed return code 139.
ABC
bug
dependencies
#4473
opened Jul 2, 2024 by
kareefardi
Can't build from 0.42 tarball
pending-verification
This issue is pending verification and/or reproduction
#4470
opened Jun 29, 2024 by
spth
support error for Aggregate Initialization and Replication
feature-request
#4462
opened Jun 18, 2024 by
yelen103
CologneChip synthesis fails silently (simulation discrepancies)
bug
#4457
opened Jun 15, 2024 by
tarik-ibrahimovic
Feature Request: Add Support for Input Filelist Option
feature-request
#4456
opened Jun 15, 2024 by
tarik-ibrahimovic
IDES4_MEM gowin module is missing
needs-info
Issue needs more context/information in order to be resolved
#4453
opened Jun 13, 2024 by
LaneaLucy
check-git-abc in Makefile for the first compile time
pending-verification
This issue is pending verification and/or reproduction
#4449
opened Jun 13, 2024 by
nlwmode
Ensuring smooth Yosys-to-Synlig compatability and tracking
feature-request
#4436
opened Jun 9, 2024 by
chili-chips-ba
Yosys Verilog Parsing Error: Unable to Synthesize After Reading File
bug
#4427
opened Jun 4, 2024 by
LoSyTe
formal: Produced traces make it look like asserts trigger a clock step too late
pending-verification
This issue is pending verification and/or reproduction
#4426
opened Jun 3, 2024 by
NikLeberg
CXXRTL: >20x compile time regression with clang -18
bug
cxxrtl
pending-verification
This issue is pending verification and/or reproduction
#4419
opened May 27, 2024 by
Wren6991
A topological loop is generated after using async2sync
pending-verification
This issue is pending verification and/or reproduction
#4414
opened May 24, 2024 by
ZhiyuanYan
Yosys right shift error
pending-verification
This issue is pending verification and/or reproduction
#4413
opened May 24, 2024 by
WeneneW
Abnormal output
pending-verification
This issue is pending verification and/or reproduction
#4407
opened May 22, 2024 by
WeneneW
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