@wstucker @Mluckydwyer @stsoe @franciscoIglesias

@franciscoIglesias @Mluckydwyer pls help me a bit. I am struggling a lot from the last month.

Our demo simply allows you to view the value of a system clock, you should see it increasing as you did. Our demo documentation is written for the included zynq_demo. It does not show how to integrate your custom SoC. To do so, you would need to create a new device tree file modeling your system and then go from there. I personally do not have much experience in that scenario, but the buildroot issues are likely due to the mapping of your SoC not being correctly configured in buildroot through the device tree file.

Thanks for replying. I did built with necessary device tree. And I checked in the runtime that that are added. But I built it with the petalinux. I am also using the zynq 702 board that I think will be the perfect thing to use that zynq_demo. Have u been able to write in that 0x40000000 address ?

Like I wanted to know whether we can write in the address ? and read the value ? Is it possible to write and read in the same address ?

In that demo there is no simulated memory setup, thus you cannot write to those addresses. You will need to augment the demo such as adding memory to it and map/binding QEMU to your desired range:

#define NR_MASTERS	2
#define NR_DEVICES	2

SC_MODULE(Top)
{
        ...	
	memory mem;
        ...
	Top(sc_module_name name, const char *sk_descr, sc_time quantum) :
		bus("bus"),
		zynq("zynq", sk_descr),
		debug("debug"),
		mem("mem", sc_time(1, SC_NS), 16),
		rst("rst")
	{
		m_qk.set_global_quantum(quantum);
		zynq.rst(rst);

		bus.memmap(0x40000000ULL, 0x100 - 1,
				ADDRMODE_RELATIVE, -1, debug.socket);
		bus.memmap(0x40000100ULL, 0x10 - 1,
				ADDRMODE_RELATIVE, -1, mem.socket);

Something along those lines should work for you. You can then use the devmem 0x40000100 32 A to write an 0xA to 0x40000100, mind you will only be able to write in the ranges specified in your bus.memmap call.

@Mluckydwyer Thanks a lot . Now it becomes more clear to me.

Suppose my address of the IP block is 0x43c30000 and when I write 0x1 data in this address , my soc ip generates 32 bit number which it sent back in the address 0x43c30010 . So in this format we can't read the address right ? as it is inside the memory range (0x100 -1 )?

So you suggest to change the actual custom PL address to 0x43c31000 ? some thing like so that I can read the value that is coming from the PL block ?

@Mluckydwyer

can you help me to add some lines I think we need to add some lines . as I am getting segmentation fault(core dumped) error while running the app.

Do we need any changes in this lines ?

zynq.m_axi_gp[0]->bind(*(bus.t_sk[0]));

	/* Connect the PL irqs to the irq_pl_to_ps wires.  */
	debug.irq(zynq.pl2ps_irq[0]);

	/* Tie off any remaining unconnected signals.  */
	zynq.tie_off();

	SC_THREAD(pull_reset);

Your NR_MASTERS may need to be 2, not 1. Have you debugged the code to see where the segmentation fault is occurring?

@Mluckydwyer Thanks for the point. FOR ME, NR_DEVICES 2 worked. is it right ?

I have a small question. I have bind two memory address one is 0x43c3000 and 0x43c30010.

In the SoC, the address 0x43c30 supposed to be returned a random number when I write 0x 1 in the address 0x43c3000.

But now I am getting only 0. Do you have any suggestion where the problem would be ? I tied this two address with mem.socket for reading from custom PL block do I have to use mem socket or debug socket ?

This was my code :

Top(sc_module_name name, const char *sk_descr, sc_time quantum) :
		bus("bus"),
		zynq("zynq", sk_descr),
		debug("debug"),
		mem1("mem1", sc_time(1, SC_NS), 16),
		mem2("mem2", sc_time(1, SC_NS), 16),
		rst("rst")
	{
		m_qk.set_global_quantum(quantum);

		zynq.rst(rst);
		bus.memmap(0x43c31000ULL, 0x100 - 1, ADDRMODE_RELATIVE, -1, debug.socket);

		bus.memmap(0x43c30010ULL, 0x100 - 1, ADDRMODE_RELATIVE, -1, mem1.socket);


		bus.memmap(0x43c30000ULL, 0x100- 1,
				ADDRMODE_RELATIVE, -1, mem2.socket);
		

		zynq.m_axi_gp[0]->bind(*(bus.t_sk[0]));
		/* Connect the PL irqs to the irq_pl_to_ps wires.  */
		debug.irq(zynq.pl2ps_irq[0]);

		/* Tie off any remaining unconnected signals.  */
		zynq.tie_off();

		SC_THREAD(pull_reset);
	}

@Mluckydwyer
I put this simple soc on the qemu

I have a simple axi bus which address is 0x43c3000 and in the address 0x43c30008 it will return 0xFFFF . How to receive this value from the IP ? can u suggest anything ?