Popular repositories Loading
-
VHDL-UARTInterface
VHDL-UARTInterface PublicVHDL codes for the transmitter and receiver modules of the implementation of an UART module.
VHDL 1
-
OpenCV-Python-ImageDetectionProject
OpenCV-Python-ImageDetectionProject PublicThe image detection implementation was used for a robot participating in a basketball shootout.
Python 1
-
Verilog-DoorLockSystem
Verilog-DoorLockSystem PublicDoor Lock system that required a certain keypad combination to be entered for it to unlock.
Verilog 1
-
Verilog-SingleCycleProcessor
Verilog-SingleCycleProcessor PublicMIPS architecture inspired processor that runs custom ISA.
Verilog 1
-
Verilog-MultiCycleProcessor
Verilog-MultiCycleProcessor PublicMIPS architecture inspired processor that runs custom ISA.
Verilog 1
-
Assembly-AudioRecorderAndPlayer
Assembly-AudioRecorderAndPlayer PublicThis is a audio recorder device that can playback the sound faster or slower to create different effects.
Assembly 1
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.