Skip to content

Pull requests: StanfordVLSI/dragonphy2

Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt click/return to exclude labels
or click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Assignee
Filter by who’s assigned
Sort

Pull requests list

cvxpy fix
#161 by sgherbst was merged Feb 5, 2021 Loading…
Phys design v2
#159 by zamyers was merged Nov 19, 2020 Loading…
Transmitter hot fix
#158 by CansWang was closed Nov 19, 2020 Loading…
Add TX multicycle constraints
#157 by sgherbst was closed Nov 19, 2020 Loading…
Phys design v2
#156 by zamyers was merged Nov 12, 2020 Loading…
Fix missing output driver information
#155 by sgherbst was merged Nov 12, 2020 Loading…
dcore hot fix
#154 by sjkim85 was closed Dec 9, 2020 Loading…
Constraints update
#153 by sgherbst was merged Nov 10, 2020 Loading…
Transmitter
#152 by CansWang was merged Nov 9, 2020 Loading…
Fix TX synthesis bug
#150 by sgherbst was merged Nov 6, 2020 Loading…
Fix non-deterministic register map
#149 by sgherbst was merged Nov 4, 2020 Loading…
Transmitter
#148 by CansWang was merged Nov 5, 2020 Loading…
output_buf module create
#146 by CansWang was merged Oct 31, 2020 Loading…
Update clock constraints for TX
#144 by sgherbst was merged Oct 30, 2020 Loading…
Physical Design Flow Datapath Updates
#142 by zamyers was merged Oct 29, 2020 Loading…
Combinational loop removed
#141 by CansWang was merged Oct 28, 2020 Loading…
prbs test & fixed pattern test added!
#138 by CansWang was merged Oct 27, 2020 Loading…
Top-level TX integration
#132 by sgherbst was merged Oct 21, 2020 Loading…
Analog core update
#129 by sjkim85 was merged Oct 15, 2020 Loading…
Transmitter
#128 by CansWang was merged Oct 17, 2020 Loading…
ProTip! What’s not been updated in a month: updated:<2024-07-19.