Skip to content
View SeahK's full-sized avatar
🐰
give me 🥕
🐰
give me 🥕

Highlights

  • Pro
Block or Report

Block or report SeahK

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Stars

Showing results

A standalone implementation of the Tethered Serial Interface (TSI) in Python.

Python 4 Updated Aug 17, 2024

This fork of GTSAM extends the idea of incremental updates, but formulates the problem in linear algebra for better performance.

C 2 1 Updated Jun 22, 2024
Scala 22 2 Updated Feb 26, 2023
Scala 6 1 Updated Aug 13, 2024

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

Python 73 49 Updated Jul 29, 2024

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Scala 854 221 Updated Aug 19, 2024

A modular, automatable, tunable mapper for accelerator programming

Python 9 1 Updated Apr 27, 2022

Fork of upstream onnxruntime focused on supporting risc-v accelerators

C 77 27 Updated Mar 26, 2023

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

C 53 38 Updated Aug 17, 2024

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Scala 1,542 611 Updated Aug 19, 2024

Berkeley's Spatial Array Generator

Scala 747 153 Updated Aug 14, 2024