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A standalone implementation of the Tethered Serial Interface (TSI) in Python.
rogerhh / gtsam
Forked from borglab/gtsamThis fork of GTSAM extends the idea of incremental updates, but formulates the problem in linear algebra for better performance.
Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
A modular, automatable, tunable mapper for accelerator programming
Fork of upstream onnxruntime focused on supporting risc-v accelerators
Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more