In packet based architectures, information is sent from one device to another through packets which contain the information. In most modern computers, the packet based PCIe standard is used to communicate between different devices in our computer, to connect devices like graphics cards, hard drives and wifi cards. Transmission between data isn’t perfect however and thus we need to implement logic to ensure data makes it to the destination, and one way we are doing this is a Replay Buffer. A Replay Buffer stores data as the sending device sends out packets. This information is received and checked for errors at the receiving end of the architecture. If the receiving device detects an error in the packet it sends a non-acknowledgement (NAK) indicating that the transmission has problems, then the Replay Buffer will resend the failed packets to the sender. However, if no error is detected the system will send an acknowledgement (ACK) that includes the packet number for the packet that was last received properly. Following this the replay buffer will purge all packets with a sequence number less than or equal to the ACK sequence value. This Repo is a repository of an attempt to recreate a replay buffer in Verilog. Made for CSUS CPE 186 Class, CPE186_Proj1 is the specs for the assignment, CPE 186 Project 1 Report is the final report for the class.