Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

RISC-V Formal Verification Framework

Resources to learn RISC-V programming

Main repo for RISC-V project class EE6894

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

Open-source high-performance RISC-V processor

RISC-V 32-bit microcontroller developed in Verilog

Read only mirror of SVN ChibiOS repository at https://sourceforge.net/projects/chibios/

A local https proxy server using docker as backend

A Verilog based 5-stage fully functional pipelined RISC-V Processor code.

RISC-V CPU Core

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Functional verification project for the CORE-V family of RISC-V cores.

RISC-V CPU Core (RV32IM)

A Linux-capable RISC-V multicore for and by the world

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. …

🌠 List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers.

The fastest RISC-V sandbox

The Ultra-Low Power RISC-V Core

A graphical processor simulator and assembly editor for the RISC-V ISA

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM and embedded RISC-V architectures.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

GNU toolchain for RISC-V, including GCC

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SCR1 is a high-quality open-source RISC-V MCU core in Verilog