This is a single board computer based on Motorola 68000. It features:

• 512kiB to 8MiB DRAM (SIMM 30 pins x2)
• basic memory protection / paging
• 8bits expansion bus with 4 slots
• PS/2 keyboard and mouse support
• serial link (TTL)
• boot with serial bootstrap or user flash

Some pictures here.

The block diagram below depicts the board architecture:

Most board glue logic is implemented with an Altera EPM7128S CPLD. This part is obsolete but modern replacement exists with Actel Microsemi Microchip ATF1508AS (never tested though). The CPLD implements:

• DRAM address multiplexing
• DRAM refresh
• basic memory management: base address translation and inbound check with power of two alignment constraints
• 8-bits expansion bus access, for 8-bits wide or 16-bits wide memory cycle from the 68000
• first stage boot procedure, by copying during reset the 512 first bytes from the flash memory (see MFP chip description below) at address 000000h in DRAM.

Expansion bus also uses a few discrete logic (74245 buffers and 74138 address decoder).

An additional 74148 encodes interrupt sources to CPU IPL0/1/2.

The CPLD provides very basic memory management capabilities, for user mode accesses only (FC2 set to 0). It relies on two value set with four registers. These registers are write only, 16-bits, but only the upper bit 15:8 are used.

Any user address is and'ed with MMU_MASK then or'ed with MMU_BASE. It results in a memory area allocated to a user program with a power of two size, with a base address aligned to its own size. Any user access that targets an address above the allocated size ends with a bus error.

The autovectored interrupt scheme is used (VPA# assertion). To save pins on the CPLD the FC0 and FC1 are not available to identify an interrupt acknowledge cycle, so any read cycle at FFFFFFh with FC2 set to 1 is considered as such.

This bus provides access to 5 peripherals:

• 4 available through dedicated connectors (2x10 female pin headers)
• 1 embeded to the board: the MFP

It provides for each peripheral up to 128kiB aperture into CPU memory space.

The table below lists the signals on this bus as seen for each slot.

This is how translates a byte access from the 68000 (UDS# or LDS# alone)

note: peripherals like the MFP ignore the address bits 16:1 and can ignore the ALE# signal.

This is how translates a 16-bits access from the 68000 (UDS# and LDS#)

Right after a reset, the CPLD starts by transfering 512 bytes of data from the MFP FLASH_DATA register into the first bytes of DRAM. Then the very first 68000 memory access (at 0000000h) is performed.

Because any software is to be much bigger than just 512-bytes, this chunk of code must itself include assembly instructions to copy the rest of the code - still accessing FLASH_DATA register.

The MFP contains two software images for the 68000:

• a serial bootstrap, loading from the serial interface the binary to jump in, that is enables by pressing 's' key on a keyboard plugged into the PS/2 port
• or an embedded binary to jump in.

To change the embedded binary, the MFP firmware must be recompiled and programmed (the 68000 binary is a constant data table within the microcontroller firmware).

This is a software defined chip base on a PIC18F27K42 microcontroller. It provides:

• embedded flash with 2 software images for the 68000, selection by detecting pressed key at reset.
• IOs/timer with dedicated low-priority interrupt: two PS/2 port, one serial link, 1 kHz RTC timer
• 250 Hz system timer with dedicated highest-priority interrupt
• hard/soft reset
• debug register (POST or so)

The MFP has only two memory locations accessible through the expansion bus: one to set the actual register to access, the other to read or write data from/to the register.

This table below is no spec, it just shows the parts that equip the board on my desk.